ECE 545. Digital System Design with VHDL

(1)

Course web page:

ECE 545

Digital System Design with VHDL

ECE web page

_→

Courses

_→

Course web pages

→

ECE 545

(2)

Kris Gaj

Office hours: Thursday, 7:30-8:30 PM,

Tuesday, 7:30-8:30 PM,

and by appointment

Research and teaching interests:

• reconfigurable computing

• computer arithmetic

• cryptography

• network security

Contact:

The Engineering Building, room 3225

kgaj@gmu.edu

(3)

ECE 545

Part of:

MS in Electrical Engineering

MS in Computer Engineering

Digital Systems Design

Fundamental course for the specialization area:

Elective

course in the remaining specialization areas

One of five core courses

(4)

ECE 545

Part of:

PhD in Electrical and Computer Engineering

Knowledge tested at the

Technical Qualifying Exam (TQE)

(5)

I am interested in…

I want to specialize primarily in…

VLSI

Digital Systems Design ASICs & FPGAs

VHDL/Verilog CAD Tools Reconfigurable Computing Microelectronics VLSI Fabrication Nanoelectronics

CAD tools & Design Automation Hardware Description Languages FPGAs & Reconfigurable computing Computer Arithmetic

Front-end ASIC Design

(algorithmic downto gate level) Back-end ASIC Design

(circuit and mask layout levels) Analog & Digital Circuit Design VLSI Fabrication

Microelectronics Nanoelectronics

Semiconductor Devices

MS CpE

Digital Systems Design

MS EE Microelectronics/ Nanoelectronics Recommended program & specialization

(6)

algorithmic

Design level

register-transfer gate transistor layout devices

Courses

Computer Arithmetic Digital System Design with VHDL Digital Integrated Circuits Physical VLSI Design VLSI Test Concepts ECE 545 ECE 645 ECE 586 ECE 680 ECE 682

ECE684 MOS Device

Electronics ECE 584 Semiconductor Device Fundamentals ECE 681 VLSI Design for ASICs

(7)

CpE

Digital Systems Design

Pre-

Approved Electives

Suggested Electives

ECE 545 Digital System Design with VHDL

ECE 586 Digital Integrated Circuits ECE 645 Computer Arithmetic

ECE 681 VLSI Design for ASICs ECE 682 VLSI Test Concepts

ECE 584, 684, … (technology)

ECE 511, 611, … (microprocessors) ECE 646, 746, … (applications)

K. Gaj, K. Hintz, H. Homayoun, J. Kaps, T. Storey

CpE

Microprocessors and Embedded Systems

ECE 510 Real-Time Concepts ECE 511 Microprocessors

ECE 611 Advanced Microprocessors ECE 612 Real-Time Embedded

Systems

ECE 641 Computer System Architecture

CS 540, 583 (languages, algorithms) CS 635 (parallel machines)

ECE 542, 642, 742 (networks) ECE 645, 681 (digital design)

ECE 548 (sequential mach. theory)

H. Homayoun, J. Kaps, P. Pachowicz, C. Sabzevari

(8)

DIGITAL SYSTEMS DESIGN

Concentration advisors: Kris Gaj, Jens-Peter Kaps, Ken Hintz

1.  ECE 545 Digital System Design with VHDL

– K. Gaj, project, FPGA design with VHDL, Aldec/Mentor Graphics, Xilinx/Altera

2. ECE 645 Computer Arithmetic

– K. Gaj, project, FPGA design with VHDL Aldec/Mentor Graphics, Xilinx/Altera

3. ECE 681 VLSI Design for ASICs

– H. Homayoun, project/lab, front-end and back-end ASIC design with Synopsys tools

4. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri,

5. ECE 682 VLSI Test Concepts – T. Storey

(9)

Grading Scheme

• Homework

- 10%

• Project

- 40%

• Midterm Exam - 20%

(10)

Midterm exam 1

ü

 

2 hours 30 minutes

ü

 

in class

ü

 

design-oriented

ü

 

open-books, open-notes

ü

 

practice exams available on the web

Last week of October

Tentative date:

(11)

Final exam

ü

 

2 hours 45 minutes

ü

 

in class

ü

 

design-oriented

ü

 

open-books, open-notes

ü

 

practice exams available on the web

Thursday, December 13, 4:30-7:15pm

Date:

(12)

12

(13)

Required Textbook

Pong P. Chu, RTL Hardware Design Using VHDL,

Wiley-Interscience, 2006.

IKC ?8I;N8I<;<J@>E LJ@E>M?;C :f[`e^]fi<]ÔZ`\eZp#GfikXY`c`kp#Xe[JZXcXY`c`kp GFE>G%:?L I KC ? 8 I ; N 8 I < ; <J @> E LJ @E > M ? ; C :?L :f[`e^]fi<]ÔZ`\eZp # Gfi kXY`c`kp #Xe[ JZXcXY`c`kp K?<JB@CCJ8E;>L@;8E:<E<<;<;KF D8JK<IIKC?8I;N8I<;<J@>E

K_`j Yffb k\XZ_\j i\X[\ij _fn kf jpjk\dXk`ZXccp [\j`ê \]ÔZ`\ek# gfikXYc\# Xe[ jZXcXYc\ I\^`jk\i KiXej]\i C\m\c IKC [`^`kXc ZìZl`kj ljè^ k_\ M?;C _Xi[nXi\ [\jZi`gk`fe cXe^lX^\ Xe[ jpek_\j`j jf]knXi\% =fZljè^ fe k_\ df[lc\$c\m\c [\j`ê# n_`Z_ `j Zfdgfj\[ f] ]leZk`feXc le`kj# iflkè^ ZìZl`k# Xe[ jkfiX^\# k_\ Yffb `ccljkiXk\j k_\ i\cXk`fej_`g Y\kn\\e k_\M?;CZfejkilZkjXe[k_\le[\icpè^_Xi[nXi\Zfdgfe\ekj#Xe[j_fnj_fnkf[\m\cfg Zf[\j k_Xk ]X`k_]lccp i\Õ\Zk k_\ df[lc\$c\m\c [\j`ê Xe[ ZXe Y\ jpek_\j`q\[ èkf \]ÔZ`\ek ^Xk\$c\m\c`dgc\d\ekXk`fe% J\m\iXcle`hl\]\Xkli\j[`jkè^l`j_k_\Yffb1 :f[è^jkpc\k_Xkj_fnjXZc\Xii\cXk`fej_`gY\kn\\eM?;CZfejkilZkjXe[ _Xi[nXi\Zfdgfe\ekj :feZ\gklXc[`XîXdjk_Xk`ccljkiXk\k_\i\Xc`qXk`fef]M?;CZf[\j <dg_Xj`jfek_\Zf[\i\lj\ GiXZk`ZXc\oXdgc\jkf[\dfejkiXk\Xe[i\è]fiZ\[\j`êZfeZ\gkj# gifZ\[li\j#Xe[k\Z_e`hl\j KnfZ_Xgk\ijfei\Xc`qè^j\hl\ek`XcXc^fi`k_djè_Xi[nXi\ KnfZ_Xgk\ijfejZXcXYc\Xe[gXiXd\k\i`q\[[\j`êjXe[Zf[è^ Fe\Z_Xgk\iZfm\iè^k_\jpeZ_ife`qXk`feXe[èk\i]XZ\Y\kn\\edlck`gc\ ZcfZb[fdXèj 8ck_fl^_k_\]fZljf]k_\Yffb`jIKCjpek_\j`j#`kXcjf\oXdè\jk_\jpek_\j`jkXjb]ifdk_\ g\ijg\Zk`m\ f] k_\ fm\iXcc [\m\cfgd\ek gifZ\jj% I\X[\ij c\Xie ^ff[ [\j`ê giXZk`Z\j Xe[ ^l`[\cè\jkf\ejli\k_XkXeIKC[\j`êZXeXZZfddf[Xk\]lkli\j`dlcXk`fe#m\i`ÔZXk`fe#Xe[ k\jkèê\\[j#Xe[ZXeY\\Xj`cpèZfigfiXk\[èkfXcXi^\ijpjk\dfii\lj\[%;`jZljj`fe`jè$ [\g\e[\ekf]k\Z_efcf^pXe[ZXeY\Xggc`\[kfYfk_8J@:Xe[=G>8[\m`Z\j% N`k_ X YXcXeZ\[ gi\j\ekXk`fe f] ]le[Xd\ekXcj Xe[ giXZk`ZXc \oXdgc\j# k_`j `j Xe \oZ\c$ c\ek k\okYffb ]fi lgg\i$c\m\c le[\iîX[lXk\ fi îX[lXk\ Zflij\j è X[mXeZ\[ [`^`kXc cf^`Z% <e^è\\ijn_fe\\[kfdXb\\]]\Zk`m\lj\f]kf[XpËjjpek_\j`jjf]knXi\Xe[=G>8[\m`Z\j j_flc[Xcjfi\]\ikfk_`jYffb%

GFE>G%:?L#G?;#`j8jjfZ`Xk\Gif]\jjfièk_\;\gXikd\ekf]<c\Zki`ZXcXe[:fdglk\i <e^è\\iè^# :c\m\cXe[ JkXk\ Le`m\ij`kp% ?\ _Xj i\Z\`m\[ îXekj ]ifd Yfk_ E8J8 Xe[ k_\ EXk`feXcJZ`\eZ\=fle[Xk`feXe[_XjkXl^_kle[\iîX[lXk\Xe[îX[lXk\$c\m\c[`^`kXcjpjk\dj Xe[Zfdglk\iXiZ_`k\Zkli\Zflij\j]fidfi\k_XeX[\ZX[\%

(14)

Supplementary Textbook – Basics Refresher

Stephen Brown and Zvonko Vranesic,

Fundamentals of Digital Logic with VHDL Design,

McGraw-Hill, 3

rd

_{or 2}

nd

_Edition

(15)

Supplementary Textbook – Advanced

Hubert Kaeslin, Digital Integrated Circuit Design:

From VLSI Architectures to CMOS Fabrication,

Cambridge University Press; 1st Edition, 2008.

Used in ECE 681

(16)

16

Technology

&

(17)

Bl ock R AMs Bl ock R AMs Configurable Logic Blocks I/O Blocks

What is an FPGA?

Block RAMs

(18)

FPGA Design process (1)

Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..

Library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity RC5_core is

port(

clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31downto0); data_output: out std_logic_vector(31downto0); out_full: in std_logic;

key_input: in std_logic_vector(31downto0); key_read: out std_logic;

);

end AES_core;

Specification / Pseudocode

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulation Synthesis

On-paper hardware design (Block diagram & ASM chart)

(19)

FPGA Design process (2)

Implementation

Configuration

Timing simulation

(20)

(21)

(22)

(23)

(24)

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC;

signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin

A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else

not B; Y<=Y1 when (NEG_Y='0') else

not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1;

with (L1 & L0) select

Y1<=MUX_0 when "00",

MUX_1 when "01", MUX_2 when "10", MUX_3 when others;

end MLU_DATAFLOW;

VHDL description

_{Circuit netlist}

(25)

FPGA Implementation

• After synthesis the entire implementation

(26)

(27)

(28)

Xilinx FPGA Tools

Aldec Active-HDL (IDE)

Xilinx XST &

Synopsys Synplify Premier Xilinx ISE Design Suite

ECE Labs

Mentor Graphics ModelSim SE Xilinx XST

&

Synopsys Synplify Premier

Xilinx ISE Design Suite (IDE) Aldec Active-HDL Design Flow Xilinx ISE Design Flow simulation synthesis implementation

(29)

Xilinx FPGA Tools

Aldec Active-HDL

Student Edition (IDE)

Xilinx XST (restricted)

Home

Aldec Active-HDL Design Flow Xilinx ISE Design Flow simulation synthesis implementation

Xilinx ISE WebPACK (restricted)

Mentor Graphics ModelSim PE

Student Edition

Xilinx XST (restricted)

Xilinx ISE WebPACK (IDE)

(30)

Altera FPGA Tools

ECE Labs

Mentor Graphics ModelSim-Altera

Altera Quartus II Subscription Edition

Altera

Design Flow

simulation

(31)

Altera FPGA Tools

Home

Mentor Graphics ModelSim-Altera Starter (restricted)

Altera Quartus II Web Edition (restricted)

Altera

Design Flow

simulation

(32)

32

(33)

Project

ü

 

semester-long

ü

 

related to the research project conducted by

Cryptographic Engineering Research Group (CERG)

at GMU

ü

 

supporting NIST (National Institute of Standards

and Technology) in the evaluation of candidates

for a new cryptographic standard

(34)

34

(35)

(36)

Cryptography is Everywhere

Buying a book on-line Withdrawing cash from ATM

Teleconferencing over Intranets

Backing up files on remote server

(37)

Cryptographic Standards Before 1997

time 1970 1980 1990 2000 2010

DES – Data Encryption Standard

1977 1999

Triple DES

SHA-1–Secure Hash Algorithm SHA-2

Secret-Key Block Ciphers

Hash Functions 1993 1995 2003 SHA 2005 NSA IBM & NSA

(38)

Why a Contest for

a Cryptographic Standard?

• Avoid back-door theories

• Speed-up the acceptance of the standard

• Stimulate non-classified research on methods of

designing a specific cryptographic transformation

• Focus the effort of a relatively small cryptographic

(39)

Cryptographic Standard Contests

time 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 AES NESSIE CRYPTREC eSTREAM SHA-3

34 stream ciphers _→ 4 HW winners + 4 SW winners

51 hash functions → 1 winner

15 block ciphers _→ 1 winner

IX.1997 X.2000

I.2000 XII.2002

V.2008

X.2007 XII.2012 XI.2004

(40)

40

Cryptographic Contests - Evaluation Criteria

Security

Software Efficiency

Hardware Efficiency

Simplicity

FPGAs ASICs

Flexibility

Licensing

(41)

Specific Challenges of Evaluations

in Cryptographic Contests

•  Very wide range of possible applications, and as a result

performance and cost targets

throughput: single Mbits/s to hundreds Gbits/s cost: single cents to thousands of dollars

•  Winner in use for the next 20-30 years, implemented using

technologies not in existence today •  Large number of candidates

•  Limited time for evaluation

(42)

Mitigating Circumstances

•  Security is a primary criterion

•  Performance of competing algorithms tend to very significantly

(sometimes as much as 500 times)

•  Only relatively large differences in performance matter

(typically at least 20%)

•  Multiple groups independently implement the same algorithms

(catching mistakes, comparing best results, etc.) •  Second best may be good enough

(43)

AES

Contest

1997-2000

(44)

Rules of the Contest

Each team submits

Detailed

cipher

specification

Justification

of design

decisions

Tentative

results

of cryptanalysis

Source

code

in C

Source

code

in Java

Test

vectors

(45)

AES: Candidate Algorithms

USA:

_Mars RC6 Twofish Safer+ HPC

Canada:

CAST-256 Deal

Costa Rica:

Frog

Australia

:

LOKI97

Japan:

E2

Korea:

Crypton

Belgium:

Rijndael

France:

DFC

Germany:

Magenta

Israel, UK,

Norway:

Serpent 8 ₄ 2 1

(46)

AES Contest Timeline

15 Candidates

CAST-256, Crypton, Deal, DFC, E2, Frog, HPC, LOKI97, Magenta, Mars, RC6, Rijndael, Safer+, Serpent, Twofish,

June 1998

August 1999

October 2000

1 winner: Rijndael

Belgium 5 final candidates

Mars, RC6, Twofish (USA) Rijndael, Serpent (Europe)

Round 1

Round 2

Security Software efficiency Security Software efficiency Hardware efficiency

(47)

Security

Simplicity

High

Adequate

Simple

Complex

NIST Report: Security & Simplicity

MARS

Rijndael

Serpent

Twofish

(48)

0

5

10

15

20

25

30 Serpent

Rijndael

RC6

Twofish

Mars

Efficiency in software: NIST-specified platform

128-bit key 192-bit key 256-bit key

200 MHz Pentium Pro, Borland C++ Throughput [Mbits/s]

(49)

NIST Report: Software Efficiency

Encryption and Decryption Speed

32-bit

processors

64-bit

processors

DSPs

high

medium

low

RC6 Rijndael Mars Twofish Serpent Rijndael Twofish Mars RC6 Serpent Rijndael Twofish Mars RC6 Serpent

(50)

Efficiency in FPGAs: Speed

0 50 100 150 200 250 300 350 400 450 500 Throughput [Mbit/s] Serpent

x8 Rijndael Twofish Serpent x1 RC6 Mars

431 444 414 353 294 177 ₁₇₃ 104 149 62 143 112 88 102 61

Worcester Polytechnic Institute University of Southern California George Mason University

(51)

0 100 200 300 400 500 600 700

Rijndael Serpent Twofish RC6 Mars x1 606 202 105 103 57 443 202 105 104 57

3-in-1 (128, 192, 256 bit) key scheduling 128-bit key scheduling

Efficiency in ASICs: Speed

(52)

Results for ASICs matched very well results for FPGAs, and were both very different than software

FPGA ASIC

Serpent fastest in hardware, slowest in software GMU+USC, Xilinx Virtex XCV-1000 NSA Team, ASIC, 0.5µm MOSIS

Lessons Learned

x8

x1

(53)

Hardware results matter!

Speed in FPGAs Votes at the AES 3 conference

Final round of the AES Contest, 2000

Lessons Learned

(54)

• Optimization for maximum throughput

• Single high-speed architecture per candidate

• No use of embedded resources of FPGAs

(Block RAMs, dedicated multipliers)

• Single FPGA family from a single vendor:

Xilinx Virtex

(55)

FPGA Evaluations

AES eSTREAM SHA-3

Multiple FPGA families No No Yes

Multiple architectures No Yes Yes

Use of embedded resources No No Yes Primary optimization target Throughput Area Throughput/ Area Throughput/ Area

Experimental results No No Yes

Availability of source codes

No No Yes

(56)

ASIC Evaluations

AES eSTREAM SHA-3

Multiple processes/ libraries

No No Yes

Multiple architectures No Yes Yes

Primary optimization target

Throughput Power x Area x Time

Throughput /Area

Post-layout results No Yes Yes

Experimental results No Yes Yes

Availability of source codes

No No Yes

(57)

Benchmarking

Tools

(58)

Tools for Benchmarking

Implementations of Cryptography

Software FPGAs ASICs

eBACS D. Bernstein (UIC) T. Lange (TUE)

?

ATHENa K. Gaj, J. Kaps, et al. (GMU) 2006-present 2009-present

(59)

59

Benchmarking

(60)

60

eBACS: ECRYPT Benchmarking of

Cryptographic Systems:

•  measurements on multiple machines (currently over 90)

•  each implementation is recompiled multiple times

(currently over 1600 times) with various compiler options •  time measured in clock cycles/byte for multiple

input/output sizes

•  median, lower quartile (25th percentile), and upper quartile

(75th_{percentile) reported}

•  standardized function arguments (common API)

SUPERCOP - toolkit developed by D. Bernstein and T. Lange for measuring performance of cryptographic software

(61)

SUPERCOP Extension for Microcontrollers –

XBX: 2009-present

Ø  Christian Wenzel-Benner,

ITK Engineering AG, Germany

Ø  Jens Gräf, LiNetCo GmbH,

Heiger, Germany

Developers:

Allows on-board timing measurements Supports at least the following

microcontrollers: 8-bit:

Atmel ATmega1284P (AVR) 32-bit:

TI AR7 (MIPS)

Atmel AT91RM9200 (ARM 920T) Intel XScale IXP420 (ARM v5TE) Cortex-M3 (ARM)

(62)

62

Benchmarking

(63)

ATHENa

–

A

utomated

T

ool for

H

ardware

E

valuatio

N

63

Open-source benchmarking environment, written in Perl, aimed at

AUTOMATED generation of OPTIMIZED results for

MULTIPLE hardware platforms.

The most recent version 0.6.2 released in June 2011.

Full features in ATHENa 1.0 to be released in 2012.

(64)

Why Athena?

64

"The Greek goddess Athena was frequently called upon to settle disputes between

the gods or various mortals.

Athena Goddess of Wisdom was

known for her superb logic and intellect.

Her decisions were usually well-considered, highly ethical, and seldom motivated

by self-interest.”

from "Athena, Greek Goddess of Wisdom and Craftsmanship"

(65)

ATHENa Server

FPGA Synthesis and Implementation Result Summary + Database Entries 2 3 HDL + scripts + configuration files 1 Database Entries Download scripts and configuration files8 Designer 4 HDL + FPGA Tools User Database query Ranking of designs 5 6

Basic Dataflow of ATHENa

0

Interfaces

(66)

Three Components of the ATHENa

Environment

• ATHENa Tool

• ATHENa Database of Results

• ATHENa Website

(67)

67

ATHENa – Database

of Results

(68)

68

ATHENa Database

(69)

69

ATHENa Database – Result View

•  Algorithm parameters

•  Design parameters

§  Optimization target

§  Architecture type

§  Datapath width

§  I/O bus widths

§  Availability of source code

§  Platform

§  Vendor, Family, Device

§  Timing

§  Maximum clock frequency

§  Maximum throughput

§  Resource utilization

§  Logic blocks (Slices/LEs/ALUTs)

§  Multipliers/DSP units

§  Tools

§  Names & versions

§  Detailed options

§  Credits

(70)

70

ATHENa Database – Compare Feature

Matching fields in grey

(71)

71

(72)

72

ATHENa Website

http://cryptography.gmu.edu/athena/

•  Download of ATHENa Tool

•  Links to related tools

SHA-3 Competition in FPGAs & ASICs

•  Specifications of candidates

•  Interface proposals

•  RTL source codes

•  Testbenches

•  ATHENa database of results

(73)

73

ATHENa Result Replication Files

•  Scripts and configuration files sufficient to easily reproduce all results (without repeating optimizations)

•  Automatically created by ATHENa for all results generated using ATHENa

•  Stored in the ATHENa Database

In the same spirit of Reproducible Research as:

•  Patrick Vandewalle1, Jelena Kovacevic2, and Martin Vetterli1 (1EPFL, 2CMU)

Reproducible research in signal processing - what, why, and how. IEEE Signal Processing Magazine, May 2009. http://rr.epfl.ch/17/ •  J. Claerbout (Stanford University)

“Electronic documents give reproducible research a new meaning,”

in Proc. 62nd Ann. Int. Meeting of the Soc. of Exploration Geophysics, 1992, http://sepwww.stanford.edu/doku.php?id=sep:research:reproducible:seg92

(74)

74