CORNERSTONE Documentation Release 2.5

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CORNERSTONE Documentation

Release 2.5

Luceda Photonics

Oct 27, 2021

1 Changelog

This changelog shows the changes in the IPKISS PDK for CORNERSTONE.

2.5

• Updated for IPKISS 3.7 2.4

• Updated SOI220nm_1550nm_TE_STRIP_2X1_MMI, SOI220nm_1550nm_TE_RIB_2X1_MMI

• Updated SOI340nm_1310nm_TE_STRIP_2X2_MMI, SOI340nm_1310nm_TE_RIB_2X2_MMI 2.3

• Added: SOI220nm_1550nm_TE_RIB_Grating_Coupler, SOI220nm_1550nm_TE_STRIP_2X1_MMI, SOI220nm_1550nm_TE_STRIP_2x2_MMI, SOI220nm_1550nm_TE_STRIP_2x1_Ysplitter, SOI220nm_1550nm_TE_STRIP_Grating_Coupler, SOI220nm_1550nm_TM_STRIP_Grating_Coupler, SOI220nm_1310nm_TE_RIB_Grating_Coupler, SOI220nm_1310nm_TE_STRIP_2X1_MMI, SOI220nm_1310nm_TE_STRIP_2x2_MMI, SOI220nm_1310nm_TE_STRIP_2x1_Ysplitter, SOI220nm_1310nm_TE_STRIP_Grating_Coupler, SOI220nm_1310nm_TM_STRIP_Grating_Coupler, SOI340nm_1550nm_TE_STRIP_Grating_Coupler, SOI340nm_1310nm_TE_STRIP_Grating_Coupler,

SOI340nm_1550nm_TE_RIB_STRIP_Apodised_Grating_Coupler, SOI340nm_1550nm_TE_RIB_RIB_Apodised_Grating_Coupler, SOI500nm_1550nm_TE_RIB_2X2_MMI, SOI500nm_1550nm_TE_RIB_Grating_Coupler and

SOI500nm_1550nm_TM_RIB_Grating_Coupler

• Updated SOI220nm_1550nm_TE_RIB_2X1_MMI, SOI220nm_1310nm_TE_RIB_2X1_MMI,

SOI220nm_1310nm_TE_RIB_2x2_MMI, SOI220nm_1310nm_TE_RIB_GC,

SOI340nm_1310nm_TE_RIB_GC, SOI340nm_1310nm_TE_STRIP_GC and

SOI500nm_1550nm_TE_RIB_2X1_MMI

• Updated SOI 500nm vfab

• Renamed SOI340nm_1550nm_TE_RIB_STRIP_Apodised_Grating_Coupler to

SOI340nm_1550nm_TE_RIB_STRIP_Apodised_Grating_Coupler

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2.2.luceda1

• Updated this PDK to be compatible with IPKISS 3.4

• Renamed OA folder to openaccess 2.2

Important: Only update of 340nm (later 220 and 500)

• Updated 340nm components

• Added 340nm components

• Added Ebeam and Blocking layers 2.1

• global: add RIB_AllPass_Ring, RIB_AddDrop_Ring, STRIP_AllPass_Ring and STRIP_AddDrop_Ring

• rename SOI220nm_1550nm_TE_RIB_Grating_Coupler_RIBTapered to . . . ._Coupler_RibTapered 2.0

Important: No backward compatibilty!

Updates in view of CORNERSTONE MPW call 11

• global: renamed all the components to make their application case (wavelength and polarization) more clear

• global: 1x2 MMI replaced by 2x1 MMI

• global: remove parametric crossings

• 220nm SOI: change the MZIs (1.5um modulator length instead of 1.8um)

• 220nm SOI: fix the predefined crossings

• 340nm SOI: change the components from Strip to Rib 1.3.0

• global: change the way to select the technology (seeSection 4)

• global: add label layer (GDS 100)

• global: add parametric crossings and rib modulator

• 220nm SOI technology: update some dimensions

• 200nm SOI devices added: fixed crossings and Mach-Zehnder modulators 1.2.0

• 500nm SOI technology variant added + example scripts

• 500nm SOI devices added: grating coupler and MMI

• PHC layer added for photonic crystal devices 1.1.0

• Updates in view of CORNERSTONE MPW call 7 1.0.1

• Fix: the predefined grating couplers now have 60 grating periods.

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1.0.0

Initial IPKISS PDK for CORNERSTONE release:

• Technology settings, drawing layers, GDSII, IPKISS Link for Siemens EDA compatibility, waveguides, MMI and grating coupler building blocks, virtual fabrication for passives.

• The technology settings (virtual fabrication) has both 220nm and 340nm SOI flavours. The device library is 220nm SOI only at this point.

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2 Introduction

2.1 Process Design Kit (PDK) based design concept

If you already know about Process Design Kits (PDKs) in general, please skip to the section Getting started.

A PDK helps to bridge the gap between the fab or foundry offering IC technology and the designer who creates an IC design in that technology, as shown byFigure 2.1. In order to create a design, the designer needs to have the library cells created by the fab available, as well as technology details required for custom design of components. A PDK is implemented for a specific set of software tools.

Fig. 2.1: Concept of a Process Design Kit (PDK)

Luceda develops such a PDK so that it can be used by the IPKISS tools (IPKISS Link for Siemens EDAorIPKISS).

To this end, in general, an IPKISS PDK has several components:

• Technology settings that allow for custom design:

– Layers for drawing on, in accordance with the foundry’s definitions.

– Design rules, which provide dimensional constraints for the design to be manufacturable.

– A design rule checking (DRC) deck, checking that the designer’s mask layout adheres to the foundry’s design rules.

– A technology description that allows to generate 2D and 3D models that can be sent to physical simulation tools such as for FDTD or mode propagation.

– Routing settings for optical waveguides and electrical wiring

• The fab’s cell library, providing validated building blocks to the designer:

– Layout models that allow to place and connect the cells in the layout. These can be ‘black-box’: the detailed layout may not be visible, only the optical and electrical I/O and the bounding box.

– Simulation models that allow for simulation and functional verification of a circuit based on these cells.

• Parametric cells for typical complex cells or repetitive tasks that a designer would like to do

• Examples and (this) manual to get started

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The combination between Luceda’s design software and the IPKISS PDK for CORNERSTONE is what enables the designer to create a design specific for the CORNERSTONE technology.

Note: In this text, the words cell, component and building block are used interchangeably. In the context of a PDK, a cell, building block or component usually delivers a specific unit function, such as a fiber coupler, splitter or phase modulator. There could also be more complex cells in the PDK library though. In the context of the user design, cell could mean any design or hierarchical part thereof.

Use case: PDK cell library based design

The IPKISS PDK for CORNERSTONE provides a library with a number of predefined cells for the C band (1550nm) and O band (1310nm). With this library available from IPKISS, the designer can create a circuit directly in code (IPKISS) or from the L-Edit GUI using drag-and-drop of devices from the library (IPKISS Link for Siemens EDA).

After placing the PDK cells, optical waveguides can be drawn in a manual or semi-automated fashion. In addition, the PDK provides the necessary settings to use picazzo, Luceda’s pcell template library with functions like ring resonators, MMIs, modulators, Mach-Zehnder interferometers, fanouts, and many more.

This approach allows for fast prototyping of designs using the CORNERSTONE technology.

Use case: Custom cell design

In a lot of cases, the user will want to design custom components and include them in the design. IPKISS provides several functions for that purpose:

• Parametric cells can be defined fully in Python script, with their parameters (properties in IPKISS), layout and simulation model.

• Basic building blocks can be virtually fabricated and sent to electromagnetic simulation tools such as FDTD and EME. IPKISS has a built-in mode solver CAMFR and provides interfaces to CST Studio suite and other 3rd party tools.

• More complex subcircuits defined in IPKISS can be simulated using the built-in compact model solver Caphe.

The designer can provide models for the basic building blocks, or generate them from simulation or measure- ment data.

• The designer can maintain the resulting parametric cells in a library and use them from the IPKISS Link for Siemens EDA environment or in an IPKISS python code design.

Use case: Using internal and 3rd party libraries

In a larger design team or in the case of consecutive design projects, a designer or a design team will typically build up their own library of subcircuits that perform specific reusable functions. Using Luceda’s software, the designer or design team can create such proprietary libraries that work together with the IPKISS PDK for CORNERSTONE.

These re-usable libraries can then be shared within the team, outside of the company or used in consecutive projects.

The designer can in this way embed and sustain design knowledge in a library, and base a new design both on the PDK as well as these internal libraries.

One step further, a designer can also acquire 3rd party libraries and use them in a design project in the same way.

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Fig. 2.2: Designing with reuseable design libraries and a PDK.

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3 Getting Started

This section explains how to load the PDK in IPKISS and basics of how to use it.

If you are unfamiliar with IPKISS, please have a look at the IPKISS documentation and samples. The documentation and samples are available from the IPKISS Control Center.

The latest IPKISS documentation is also available online athttp://docs.lucedaphotonics.com/index.html.

3.1 Extracting the PDK

The PDK is distributed as a zip file, which you can extract with the unzip utility of your choice (unzip, WinZip, 7-zip, . . . ).

For the purpose of this manual, we assume you have unzipped “cornerstone-2.5.zip” as C:\temp\cornerstone.

You can inspect the directory structure of the PDK:

• data/: Contains GDS files of some fixed cells

• docs/: Contains this file

• docs/examples/scripts: Example IPKISS python scripts

• docs/examples/lib.defs: Example of IPKISS Link for Siemens EDA design project

• ipkiss/: IPKISS technology, pcells, models and functions (Python)

• openaccess/: Design libraries

• openaccess/cornerstone/: OpenAccess database for the PDK (L-Edit)

• techfiles/: Tech files (layers, display) for various tools

• techfiles/klayout/: Layer settings for KLayout GDSII visualization

3.2 Using the PDK with IPKISS Link for Siemens EDA

You can follow the instructions given in our documentationhttp://docs.lucedaphotonics.com/ipkisseda/ledit/tutorial_

pdk_based_circuit/index.html.

3.3 Using the PDK with IPKISS

Setting up the editor environment

You can follow the instructions given in our documentation http://docs.lucedaphotonics.com/latest/tutorials/

environment_setup/create_project_pdk.html.

Examples

The PDK comes bundled with a series of examples for use in IPKISS, in the C:\temp\cornerstone\docs\examples\scripts folder. These are executable Python files. The examples are a good starting point to learn how to design with the IPKISS PDK for CORNERSTONE. Below is a summary of the shipped examples:

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Example name Description

example_layers.py Visualize all the layers that are available in the cornerstone technology exam-

ple_waveguides.py

Visualize the waveguides available in the cornerstone technology

example_heater.py Example of a waveguide with a heater filament exam-

ple_design_passive.py

Example of a parameter sweep of ring resonators with automated fiber coupler embedding

exam-

ple_modulator_vfab.py

Example of a cross section visualization for one of the fixed MZM

exam-

ple_customcell.py

Create a custom PCell in IPKISS using the CORNERSTONE technology

exam-

ple_phc_soi220.py

Example of a photonic crystal component using the Luceda picazzo3 library for 220nm platform

exam-

ple_components_220.py

Shows the PDK components for 220nm platform

exam-

ple_phc_soi340.py

exam-

ple_phc_soi500.py

exam-

References

• IPKISS documentation:http://docs.lucedaphotonics.com/latest/index.html

• Library organization: http://docs.lucedaphotonics.com/latest/ipkisseda/libraries/library_organization/index.

html

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4 Technology settings

The PDK contains layer definitions and virtual fabrication settings for the 220nm, 340nm and 500nm SOI processes.

Refer to the CORNERSTONE design rule manual and MPW call documents for detailed information.

4.1 Selecting the target technology

One PDK is used to target all the technologies. At the start of an Ipkiss script, you can import the library corresponding to the technology variant you need.

For example, the 220nm SOI process:

import cornerstone_soi220.all as cornerstone

This sets the virtual fabrication process of the 220nm SOI process and imports only the process specific components and the generic pcells.

Table 4.1: List of processes

Process Library Specific cells prefix 220nm SOI cornerstone_soi220 SOI220nm

340nm SOI cornerstone_soi340 SOI340nm 500nm SOI cornerstone_soi500 SOI500nm

4.2 Layers

The following table gives an overview of the available layers and how they are named in Ipkiss. See the CORNER- STONE design rules manual for further information about the layers defined by CORNERSTONE.

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Table 4.2: Layer Table

Layer name Description IPKISS Layer GDS

Number

WG Silicon Etch - Waveguides (Light field) TECH.PPLAYER.WG 3/0

WG_HOL Silicon Etch - Waveguides (Dark field) TECH.PPLAYER.WG_HOL 4/0

GRAT Silicon Etch - Gratings TECH.PPLAYER.GRAT 6/0

SLAB Silicon Etch - Rib Protect TECH.PPLAYER.SLAB 5/0

P Low Dose p-type Implant TECH.PPLAYER.P 7/0

N Low Dose n-type Implant TECH.PPLAYER.N 8/0

PPLUS High Dose p-type Implant TECH.PPLAYER.PPLUS 9/0

NPLUS High Dose n-type Implant TECH.PPLAYER.NPLUS 11/0

VIA Vias - rounded features corners TECH.PPLAYER.VIA 12/0

M1 Electrodes - min gap between features = 2µm TECH.PPLAYER.M1 13/0

HT Heater Filaments TECH.PPLAYER.HT 39/0

PAD Heater Contact Pads TECH.PPLAYER.PAD 41/0

PHC Silicon Etch - Photonic Crystals TECH.PPLAYER.PHC 42/0

EBEAM E-beam etch layer TECH.PPLAYER.EBEAM 60/0

BLOCK Protection layer for waveguide etch TECH.PPLAYER.BLOCK 61/0

CELL Cell Outline TECH.PPLAYER.NONE.CELL 99/0

BLEED Bleed Area TECH.PPLAYER.NONE.BLEED 98/0

LBL Label - DRC purpose layer then included in GDS 4

TECH.PPLAYER.NONE.LBL 100/0

STRIP_TRACE Strip waveguide routing - Luceda non-tapeout layer

TECH.PPLAYER.STRIP_TRACE

RIB_TRACE Rib waveguide routing - Luceda non-tapeout layer

TECH.PPLAYER.RIB_TRACE

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5 Components

5.1 Which components are available to use from the IPKISS PDK for CORNER- STONE?

The IPKISS PDK for CORNERSTONE contains a number of predefined components that have been tested by the fab, as well as predefined waveguide templates. In addition, Luceda has provided a number of parametric cells to make life of a designer easier.

Users can use these components and mix them with their own custom designed components to create larger circuits.

5.2 How to use IPKISS PDK for CORNERSTONE components?

An example of how to instantiate (or place) PDK components in IPKISS, you may refer the sample located at:

<path_to_installed_PDK>\cornerstone\docs\examples\scripts\example_components.py

For 340nm SOI, refer to the example at <path_to_installed_PDK>\cornerstone\examples\scripts\example_components_soi340.py With IPKISS, you may execute the sample Python code. In order to learn how to execute an IPKISS code, please refer

to section IPKISS.

If you use IPKISS Link for Siemens EDA, you will be able to use your mouse to drag-and-drop the components in L-Edit. The explanation can be found in section IPKISS Link for Siemens EDA.

Waveguide template components

Waveguide trace template are used to define how the connecting waveguides between the devices should be like. It contains the technology information on the layers and geometrical drawing of a specific type of waveguide, such as wire or rib waveguides.

Using the waveguide trace template, when users define the waveguide type at a device port and the connection line with another device, the waveguide will be generated with the corresponding waveguide type at the port it connects to. There are also devices that are drawn using the waveguide template as a layout parameter. It is useful in this case to change the device design by updating the waveguide template.

Two waveguide templates are predefined in the PDK: StripWaveguideTemplate, for strip waveguides fully etched to the BOX, and RibWaveguideTemplate for rib waveguides with a thin SOI slab remaining. Both have a default width of 400nm for O band and 450nm for C band.

These templates have no models yet.

5.3 Luceda picazzo components

Besides the component library provided by the foundry, users are also able to use the component templates from IPKISS’ Picazzo library.

Note: Unlike the IPKISS PDK for CORNERSTONE components of which device performance is characterized and guaranteed by the fab, the Picazzo library components are up to the user to ensure compatibility with the design rules and the designed device manufacturability and performance.

The list of Picazzo library components and their documentation can be found in the IPKISS manual: http://docs.

lucedaphotonics.com/latest/picazzo/

In the documentation examples, we use the silicon_photonics as the technology library (a demo technology library from IPKISS). Now that we have a real-world PDK, we are able to use it as the technology library for the picazzo design.

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Photonic crystals

Picazzo offers a lot of components for drawing photonic crystals:http://docs.lucedaphotonics.com/latest/picazzo/phc/

index.htmlThese however need some customization in order to work with CORNERSTONE: the SOI slab area needs to be explicitly added.

For 220nm SOI, an example is in <path_to_installed_PDK>\docs\examples\scripts\example_phc_soi220.py.

For 340nm SOI, an example is in <path_to_installed_PDK>\docs\examples\scripts\example_phc_soi340.py For 500nm SOI, an example is in <path_to_installed_PDK>\docs\examples\scripts\example_phc_soi500.py

5.4 How to customize a component design?

Users can also choose start a component design from scratch, instead of starting from a CORNERSTONE library component or picazzo library component.

An example is given in <path_to_installed_PDK>\docs\examples\scripts\example_customcell.py.

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6 Component List

These components have no models yet.

6.1 Grating Couplers

RIB_Grating_Coupler

PCell for Grating Coupler in rib waveguide

40 30 20 10 0 10 20 30

15 10 5 0 5 10 15

in vertical_in out

Ports

Name Type Position Angle Waveguide Template Inclination

in Optical (-21.0,0.0) 180.0 RibWaveguideTemplate 0.0

out Optical (21.0,0.0) 0.0 RibWaveguideTemplate 0.0

vertical_in Optical (0.0,0.0) 180.0 90.0

Layout Parameters

socket_width: float and number > 0 Width of the grating socket [um]

line_length: float and number > 0 length of the grating trenches (perpendicular to the socket waveguide) line_width: float and number > 0 width of the grating trenches, drawn in the given layer

n_o_periods: int and number > 0 number of periods of the grating origin: Coord2 local origin of the grating (first trench)

period: float and number > 0 period of the grating

socket_length: float and number > 0 length of the straight waveguide socket

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STRIP_Grating_Coupler

PCell for Grating Coupler in strip waveguide

40 30 20 10 0 10 20 30

15 10 5 0 5 10 15

in vertical_in out

Ports

in Optical (-25.0,0.0) 180.0 StripWaveguideTemplate 0.0

out Optical (25.0,0.0) 0.0 StripWaveguideTemplate 0.0

socket_width: float and number > 0 line_length: float and number > 0 length of the grating trenches (perpendicular to the socket waveguide)

line_width: float and number > 0 width of the grating trenches, drawn in the given layer n_o_periods: int and number > 0 number of periods of the grating

origin: Coord2 local origin of the grating (first trench) period: float and number > 0 period of the grating

socket_length: float and number > 0 length of the straight waveguide socket

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220 nm SOI cells

SOI220nm_1550nm_TE_RIB_Grating_Coupler TE C-band rib grating coupler.

100 0 100 200 300 400

20 0 20 40 60 80

out in vertical_in

Ports

SOI220nm_1550nm_TE_STRIP_Grating_Coupler TE C-band strip grating coupler.

Ports

SOI220nm_1550nm_TM_STRIP_Grating_Coupler TM C-band strip grating coupler.

Ports

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SOI220nm_1310nm_TE_RIB_Grating_Coupler TE O-band rib grating coupler.

Ports

SOI220nm_1310nm_TE_STRIP_Grating_Coupler TE O-band strip grating coupler.

Ports

SOI220nm_1310nm_TM_STRIP_Grating_Coupler TM O-band strip grating coupler.

Ports

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100 0 100 200 300 400

20 0 20 40 60 80

out in vertical_in

Ports

SOI340nm_1550nm_TM_RIB_Grating_Coupler TM C-band rib grating coupler.

Ports

SOI340nm_1550nm_TE_STRIP_Grating_Coupler TE C-band strip grating coupler.

Ports

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SOI340nm_1310nm_TE_RIB_Grating_Coupler TE O-band rib grating coupler.

Ports

SOI340nm_1310nm_TM_RIB_Grating_Coupler TM O-band rib grating coupler.

Ports

SOI340nm_1310nm_TE_STRIP_Grating_Coupler TE O-band strip grating coupler.

Ports

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SOI340nm_1550nm_TE_STRIP_Apodised_Grating_Coupler TE C-band apodised strip grating coupler using e-beam.

0 100 200 300 400

20 0 20 40 60 80

out vertical_in

Ports

SOI340nm_1550nm_TE_RIB_Apodised_Grating_Coupler TE C-band apodised rib grating coupler using e-beam.

Ports

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100 0 100 200 300 400

20 0 20 40 60 80

out in vertical_in

Ports

SOI500nm_1550nm_TM_RIB_Grating_Coupler TM C-band rib grating coupler.

Ports

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6.2 Multi Mode Interferometers

Parametric cells RIB_2x1_MMI

PCell for 2x1 MMI in rib waveguide

30 20 10 0 10 20 30 40 50

20 15 10 5 0 5 10 15 20

in1in2 out

Ports

in1 Optical (-20.0,-1.0) 180.0 RibWaveguideTemplate 0.0

in2 Optical (-20.0,1.0) 180.0 RibWaveguideTemplate 0.0

port_width: float and number > 0 Width of port [um]

taper_width: float and number > 0 Width of taper [um]

trace_spacing: float and Real, number and number >= 0 Offset between the traces at the input and the output mmi_width: float and number > 0 Width of the MMI [um]

length: float and number > 0 Length of the MMI

transition_length: ( float and Real, number and number >= 0 ), None allowed Length of the transition. Set to None to take the standard transition length.

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RIB_2x2_MMI

PCell for 2x2 MMI in rib waveguide

30 20 10 0 10 20 30 40 50

15 10 5 0 5 10 15

in1in2

out1out2

Ports

out1 Optical (45.0,-1.0) 0.0 RibWaveguideTemplate 0.0

out2 Optical (45.0,1.0) 0.0 RibWaveguideTemplate 0.0

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STRIP_2x1_MMI

PCell for 2x1 MMI in strip waveguide

20 10 0 10 20 30 40

7.5 5.0 2.5 0.0 2.5 5.0 7.5 10.0

in1

in2 out

Ports

in1 Optical (-10.0,-1.0) 180.0 StripWaveguideTemplate 0.0

in2 Optical (-10.0,1.0) 180.0 StripWaveguideTemplate 0.0

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STRIP_2x2_MMI

PCell for 2x2 MMI in strip waveguide

20 10 0 10 20 30 40

7.5 5.0 2.5 0.0 2.5 5.0 7.5 10.0

in1 in2

out1 out2

Ports

out1 Optical (35.0,-1.0) 0.0 StripWaveguideTemplate 0.0

out2 Optical (35.0,1.0) 0.0 StripWaveguideTemplate 0.0

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SOI220nm_1550nm_TE_RIB_2X1_MMI C-band 50/50 splitting 2x1 rib MMI

Ports

SOI220nm_1550nm_TE_RIB_2x2_MMI C-band 50/50 splitting 2x2 rib MMI

Ports

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SOI220nm_1550nm_TE_STRIP_2X1_MMI C-band 50/50 splitting 2x1 strip MMI

Ports

SOI220nm_1550nm_TE_STRIP_2x2_MMI C-band 50/50 splitting 2x2 strip MMI

Ports

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SOI220nm_1310nm_TE_RIB_2X1_MMI O-band 50/50 splitting 2x1 rib MMI

Ports

SOI220nm_1310nm_TE_RIB_2x2_MMI O-band 50/50 splitting 2x2 rib MMI

Ports

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SOI220nm_1310nm_TE_STRIP_2X1_MMI O-band 50/50 splitting 2x1 strip MMI

Ports

SOI220nm_1310nm_TE_STRIP_2x2_MMI O-band 50/50 splitting 2x2 strip MMI

Ports

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SOI340nm_1550nm_TE_RIB_2X1_MMI C-band 50/50 splitting 2x1 MMI

Ports

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SOI340nm_1550nm_TE_STRIP_2X1_MMI C-band 50/50 splitting strip 2x1 MMI

Ports

SOI340nm_1550nm_TE_STRIP_2X2_MMI C-band 50/50 splitting strip 2x2 MMI

Ports

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SOI340nm_1310nm_TE_RIB_2X1_MMI O-band 50/50 splitting 2x1 MMI

Ports

SOI340nm_1310nm_TE_RIB_2X2_MMI O-band 50/50 splitting 2x2 MMI

Ports

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SOI340nm_1310nm_TE_STRIP_2X1_MMI O-band 50/50 splitting strip 2x1 MMI

Ports

SOI340nm_1310nm_TE_STRIP_2X2_MMI O-band 50/50 splitting strip 2x2 MMI

Ports

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Ports

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6.3 Crossings

SOI220nm_1550nm_TE_RIB_Waveguide_Crossing Waveguide crossing in rib waveguide for the C band

8 6 4 2 0 2 4 6 8

east north

west

south

Ports

east Optical (4.62,0.0) 0.0 RibWaveguideTemplate 0.0

north Optical (0.0,4.62) 90.0 RibWaveguideTemplate 0.0

west Optical (-4.62,0.0) 180.0 RibWaveguideTemplate 0.0

south Optical (0.0,-4.62) -90.0 RibWaveguideTemplate 0.0

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SOI220nm_1310nm_TE_RIB_Waveguide_Crossing Waveguide crossing in rib waveguide for the O band

8 6 4 2 0 2 4 6 8

east north

west

south

Ports

east Optical (4.62,0.0) 0.0 RibWaveguideTemplate 0.0

north Optical (0.0,4.62) 90.0 RibWaveguideTemplate 0.0

west Optical (-4.62,0.0) 180.0 RibWaveguideTemplate 0.0

south Optical (0.0,-4.62) -90.0 RibWaveguideTemplate 0.0

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SOI220nm_1550nm_TE_STRIP_Waveguide_Crossing Waveguide crossing in strip waveguide for the C band

8 6 4 2 0 2 4 6 8

east north

west

south

Ports

east Optical (4.62,0.0) 0.0 StripWaveguideTemplate 0.0

north Optical (0.0,4.62) 90.0 StripWaveguideTemplate 0.0

west Optical (-4.62,0.0) 180.0 StripWaveguideTemplate 0.0

south Optical (0.0,-4.62) -90.0 StripWaveguideTemplate 0.0

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SOI220nm_1310nm_TE_STRIP_Waveguide_Crossing Waveguide crossing in strip waveguide for the O band

8 6 4 2 0 2 4 6 8

east north

west

south

Ports

east Optical (4.235,0.0) 0.0 StripWaveguideTemplate 0.0

north Optical (0.0,4.235) 90.0 StripWaveguideTemplate 0.0

west Optical (-4.235,0.0) 180.0 StripWaveguideTemplate 0.0

south Optical (0.0,-4.235) -90.0 StripWaveguideTemplate 0.0

(39)

6.4 Ring Filters

RIB_AllPass_Ring

PCell for All-Pass Ring filter in rib wavegudie

80 60 40 20 0 20 40 60 80

60 40 20 0 20 40 60

in out

Ports

in Optical (-30.2,-25.68) 180.0 RibWaveguideTemplate 0.0

out Optical (30.2,-25.68) 0.0 RibWaveguideTemplate 0.0

coupler_length: float and Real, number and number >= 0 Straight coupling part length [um]

coupler_spacing: float and number > 0 Centerline-to-centerline spacing of the coupler [um]

ring_length: float and number > 0 Total ring length (min of 2 * (pi*bend_radius + coupler_length))[um]

width: float and number > 0 Width of the waveguide [um]

bend_radius: float and number > 0 Bend radius for the auto-generated bends.

(40)

RIB_AddDrop_Ring

PCell for Add-Drop Ring filter in rib wavegudie

80 60 40 20 0 20 40 60 80

60 40 20 0 20 40 60

in1 out1

in2 out2

Ports

in2 Optical (30.2,25.68) 0.0 RibWaveguideTemplate 0.0

out2 Optical (-30.2,25.68) 180.0 RibWaveguideTemplate 0.0

bottom_coupler_spacing: float and number > 0 Centerline-to-centerline spacing of the bottom coupler [um]

coupler_length: float and Real, number and number >= 0 Straight coupling length [um]

top_coupler_spacing: float and number > 0 Centerline-to-centerline spacing of the top coupler [um]

(41)

(42)

STRIP_AllPass_Ring

PCell for All-Pass Ring filter in strip wavegudie

20 15 10 5 0 5 10 15 20

15 10 5 0 5 10 15

in out

Ports

in Optical (-10.2,-10.68) 180.0 StripWaveguideTemplate 0.0

out Optical (10.2,-10.68) 0.0 StripWaveguideTemplate 0.0

coupler_length: float and Real, number and number >= 0 Straight coupling part length [um]

coupler_spacing: float and number > 0 Centerline-to-centerline spacing of the coupler [um]

(43)

STRIP_AddDrop_Ring

PCell for Add-Drop Ring filter in strip wavegudie

20 15 10 5 0 5 10 15 20

15 10 5 0 5 10 15

in1 out1

in2 out2

Ports

in2 Optical (10.2,10.68) 0.0 StripWaveguideTemplate 0.0

out2 Optical (-10.2,10.68) 180.0 StripWaveguideTemplate 0.0

bottom_coupler_spacing: float and number > 0 Centerline-to-centerline spacing of the bottom coupler [um]

coupler_length: float and Real, number and number >= 0 Straight coupling length [um]

top_coupler_spacing: float and number > 0 Centerline-to-centerline spacing of the top coupler [um]

(44)

(45)

6.5 Modulators

SOI220nm_1550nm_TE_MZI_Modulator

Mach-Zehnder Modulator with fixed dimensions in rib waveguide for the C band

500 0 500 1000 1500 2000 2500

400 200 0 200 400 600 800

in out1out2

elec_1_botelec_2_botelec_3_botelec_4_botelec_5_bot

elec_1_topelec_2_topelec_3_topelec_4_topelec_5_top

Ports

in Optical (0.0,0.0) 180.0 RibWaveguideTemplate 0.0

out1 Optical (1873.4,-

1.015)

0.0 RibWaveguideTemplate 0.0

elec_1_bot Electrical (-260.8,- 369.05)

None ElectricalWireTemplate 0.0

elec_4_bot Electrical (39.2,-369.05) None ElectricalWireTemplate 0.0 elec_5_bot Electrical (139.2,-

369.05)

elec_1_top Electrical (1729.2,275.95) None ElectricalWireTemplate 0.0 elec_2_top Electrical (1829.2,275.95) None ElectricalWireTemplate 0.0 elec_3_top Electrical (1929.2,275.95) None ElectricalWireTemplate 0.0 elec_4_top Electrical (2029.2,275.95) None ElectricalWireTemplate 0.0 elec_5_top Electrical (2129.2,275.95) None ElectricalWireTemplate 0.0

(46)

SOI220nm_1550nm_TE_MZI_Modulator

Mach-Zehnder Modulator with fixed dimensions in rib waveguide for the C band

500 0 500 1000 1500 2000 2500

400 200 0 200 400 600 800

in out1out2

elec_1_botelec_2_botelec_3_botelec_4_botelec_5_bot

elec_1_topelec_2_topelec_3_topelec_4_topelec_5_top

Ports

out1 Optical (1873.4,-

1.015)

0.0 RibWaveguideTemplate 0.0

elec_4_bot Electrical (39.2,-369.05) None ElectricalWireTemplate 0.0 elec_5_bot Electrical (139.2,-

369.05)

elec_1_top Electrical (1729.2,275.95) None ElectricalWireTemplate 0.0 elec_2_top Electrical (1829.2,275.95) None ElectricalWireTemplate 0.0 elec_3_top Electrical (1929.2,275.95) None ElectricalWireTemplate 0.0 elec_4_top Electrical (2029.2,275.95) None ElectricalWireTemplate 0.0 elec_5_top Electrical (2129.2,275.95) None ElectricalWireTemplate 0.0

(47)

RIB_Modulator

Rib Modulator with parameters to set up the implants and the metal.

100 0 100 200 300 400 500

50 25 0 25 50 75 100 125

in out

elec_n elec_p

Ports

elec_n Electrical (250.0,-28.35) None ElectricalWireTemplate 0.0 elec_p Electrical (250.0,28.35) None ElectricalWireTemplate 0.0

core_width: float and number > 0 width of the core

high_dose_n_offset: float offset from the center line of high dose N implant high_dose_n_width: float and number > 0 width of high dose N implant high_dose_p_offset: float offset from the center line of high dose P implant high_dose_p_width: float and number > 0 width of high dose P implant length: float and number > 0 length of the PN junction

m1_n_offset: float offset from the center line of metal on the N implant m1_n_width: float and number > 0 width of metal on the N implant m1_p_offset: float offset from the center line of metal on the P implant m1_p_width: float and number > 0 width of metal on the P implant n_offset: float offset from the center line of low dose N implant n_width: float and number > 0 width of low dose N implant p_offset: float offset from the center line of low dose P implant p_width: float and number > 0 width of low dose P implant slab_width: float and number > 0 width of the slab

via_n_offset: float offset from the center line of vias etch on N implant via_p_offset: float offset from the center line of vias etch on P implant

(48)

via_width: float and number > 0 width of vias etch (same on both side of the center line)

(49)

6.6 Heaters

A number of parametric cells are defined to assist the designer in creating heater filaments and metallization:

HeaterFilament Parameters

trace_template: PCell and ElectricalWireTemplate

20 0 20 40 60 80 100

5 0 5 10 15 20

in out

Ports

in Electrical (0.45,0.0) None HeaterFilamentTemplate 0.0

out Electrical (99.55,-0.0) None HeaterFilamentTemplate 0.0

shape: Shape Shape from which the Trace is calculated

Examples

import cornerstone.all as cornerstone_lib import ipkiss3.all as i3

from picazzo3.routing.place_route import PlaceComponents filament = cornerstone_lib.HeaterFilament()

filament_sh = i3.ShapeArc(radius=10., start_angle=200., end_angle=340.) filament.Layout(shape=filament_sh)

contact_wedge = cornerstone_lib.HeaterWedge() contact_wedge.Layout(end_width=60., length=40.) contact_pad = cornerstone_lib.HeaterPad() contact_pad.Layout(height=60., width=60.) contacted_heater = PlaceComponents(

name="contacted_heater", child_cells={

"filament": filament,

"wedge_west": contact_wedge,

"wedge_east": contact_wedge,

"pad_west": contact_pad,

"pad_east": contact_pad }

(continues on next page)

(50)

(continued from previous page) )

contacted_heater_lo = contacted_heater.Layout(child_transformations={

"filament": (0., 0.),

"wedge_west": i3.Rotation(rotation=180.) + i3.Translation(filament_sh[0]),

"pad_west": filament_sh[0] - i3.Coord2((70., 0.)),

"wedge_east": filament_sh[-1],

"pad_east": filament_sh[-1] + i3.Coord2((70., 0.)) }

)

contacted_heater_lo.visualize()

100 50 0 50 100

20

0

20

(51)

StraightHeaterFilament Parameters

trace_template: PCell and ElectricalWireTemplate

40 20 0 20 40 60 80 100

5 0 5 10 15 20 25

in out

Ports

in Electrical (0.45,0.0) None HeaterFilamentTemplate 0.0

out Electrical (99.55,-0.0) None HeaterFilamentTemplate 0.0

length: float and number > 0

(52)

HeaterWedge

0 10 20 30 40 50

20 10 0 10 20

end_width: float and number > 0 length: float and number > 0 tip_width: float and number > 0

(53)

HeaterPad

40 30 20 10 0 10 20 30 40

40 20 0 20 40

pad

Ports

(54)

pad Electrical (0.0,0.0) None ElectricalWireTemplate 0.0

height: float and number > 0 width: float and number > 0

(55)

6.7 Y-Splitters

Ysplitter

Parameters

trace_template: PCell and _WaveguideTemplate Trace template of the Y-splitter (Strip by default)

0 20 40 60 80

20 10 0 10 20 30 40 50

in

out1 out2

Ports

in Optical (0.0,0.0) 180.0 StripWaveguideTemplate 0.0

Layout

(56)

Parameters

length: float and number > 0 Length of sbend [um]

straight_length: float and number > 0 Length of straight sections [um]

width: float and number > 0 Width of the waveguide (only used if no trace_template provided) [um]

SOI220nm_1550nm_TE_STRIP_2x1_Ysplitter TE Y splitter in strip waveguide for the C band Ports

SOI220nm_1310nm_TE_STRIP_2x1_Ysplitter TE Y splitter in strip waveguide for the O band Ports

CORNERSTONE Documentation Release 2.5