More advanced latch control circuits

In previous chapters we have only considered 4-phase bundled-data hand- shake latches using a latch controller consisting of a C-element and an inverter (figure 2.9 on page 18). In [41] this circuit is called a simple latch controller, and in [77] it is called an un-decoupled latch controller.

When a pipeline or FIFO that uses the simple latch controller fills, every second handshake latch will be holding a valid token and every other hand-

EN L EN L EN L EN L EN L E D3 E D2 E D1 Ack Req Data Ack Req EN L Data (b) (a) C C C C C C

Figure 7.4. (a) A FIFO based on handshake latches, and (b) its implementation using simple latch controllers and level-sensitive latches. The FIFO fills with valid data in every other latch. A latch is transparent when EN
0 and it is opaque (holding data) when EN
1.

Ack Req Data Ack Req Data D3 D2 D1 EN EN EN

Latch Latch Latch control control control

Figure 7.5. A FIFO where every level-sensitive latch holds valid data when the FIFO is full. The semi-decoupled and fully-decoupled latch controllers from [41] allow this behaviour.

shake latch will be holding an empty token as illustrated in figure 7.4(a) – the static spread of the pipeline is S
2.

This token picture is a bit misleading. The empty tokens correspond to the return-to-zero part of the handshaking and in reality the latches are not “holding empty tokens” – they are transparent, and this represents a waste of hardware resource.

Ideally one would want to store a valid token in every level-sensitive latch as illustrated in figure 7.5 and just “add” the empty tokens to the data stream on the interfaces as part of the handshaking. In [41] Furber and Day explain the design of two such improved 4-phase bundled-data latch control circuits: a semi-decoupled and a fully-decoupled latch controller. In addition to these specific circuits the paper also provides a nice illustration of the use of STGs for designing control circuits following the approach explained in chapter 6. The three latch controllers have the following characteristics:

The simple or un-decoupled latch controller has the problem that new input data can only be latched when the previous handshake on the out- put channel has completed, i.e., after Aout . Furthermore, the hand-

shakes on the input and output channels interact tightly: RoutAin

and Rout Ain .

The semi-decoupled latch controller relaxes these requirements some- what: new inputs may be latched after Rout , and the controller may

produce Ainindependently of the handshaking on the output channel –

the interaction between the input and output channels has been relaxed to: AoutAin.

The fully-decoupled latch controller further relaxes these requirements: new inputs may be latched after Aout (i.e. as soon as the downstream

latch has indicated that it has latched the current data), and the hand- shaking on the input channel may complete without any interaction with the output channel.

Another potential drawback of the simple latch controller is that it is unable to take advantage of function blocks with asymmetric delays as explained in

Latch controller Static spread, S Period, P “Simple” 2 2Lr2Lf
V “Semi-decoupled” 1 2Lr2Lf
V “Fully-decoupled” 1 2LrLf
V Lf
E

Table 7.1. Summary of the characteristics of the latch controllers in [41].

section 4.4.1 on page 52. The fully-decoupled latch controller presented in [41] does not have this problem. Due to the decoupling of the input and out- put channels the dependency graph critical cycle that determines the period, P, only visits nodes related to two neighbouring pipeline stages and the period be- comes minimum (c.f. section 4.4.1). Table 7.1 summarizes the characteristics of the simple, semi-decoupled and fully-decoupled latch controllers.

All of the above-mentioned latch controllers are “normally transparent” and this may lead to excessive power consumption because inputs that make multiple transitions before settling will propagate through several consecutive pipeline stages. By using “normally opaque” latch controllers every latch will act as a barrier. If a handshake latch that is holding a bubble is exposed to a token on its input, the latch controller switches the latch into the transpar- ent mode, and when the input data have propagated safely into the latch, it will switch the latch back into the opaque mode in which it will hold the data. In the design of the asynchronous MIPS processor reported in [23] we expe- rienced approximately a 50 % power reduction when using normally opaque latch controllers instead of normally transparent latch controllers.

Figure 7.6 shows the STG specification and the circuit implementation of the normally opaque latch controller used in [23]. As seen from the STG there is quite a strong interaction between the input and output channels, but the dependency graph critical cycle that determines the period only visits nodes related to two neighbouring pipeline stages and the period is minimum. It may be necessary to add some delay into the Ltto Routpath in order to ensure

that input signals have propagated through the latch before Rout. Further-

more the duration of the Lt
0 pulse that causes the latch to be transparent is

determined by gate delays in the latch controller itself, and the pulse must be long enough to ensure safe latching of the data. The latch controller assumes a broad data-validity scheme on its input channel and it provides a broad data- validity scheme on its output channel.

7.4.

Summary

This chapter introduced a selection of channel types, data-validity schemes and a selection of latch controllers. The presentation was rather brief; the aim was just to present the basics and to introduce some of the many options and

Lt = 0: Latch is transparant Lt = 1: Latch is opaque (holding data)

C C C C + + + + B EN Rin+ Rout+ Ain+ Rin- Ain- Aout- Rout- Aout+ Lt- B+ B- Lt+ Lt Rout Aout Rin Ain Latch Lt Rin Ain Rout Aout Din Dout

Figure 7.6. The STG specification and the circuit implementation of the normally opaque fully-decoupled latch controller from [23].

possibilities for optimizing the circuits. The interested reader is referred to the literature for more details.

Finally a warning: the static data-flow view of asynchronous circuits pre- sented in chapter 3 (i.e. that valid and empty tokens are copied forward con- trolled by the handshaking between latch controllers) and the performance analysis presented in chapter 4 assume that all handshake latches use the sim- ple normally transparent latch controller. When using semi-decoupled or fully- decoupled latch controllers, it is necessary to modify the token flow view, and to rework the performance analysis. To a first order one might substitute each semi-decoupled or fully-decoupled latch controller with a pair of simple latch controllers. Furthermore a ring need only include two handshake latches if semi-decoupled or fully-decoupled latch controllers are used.