Partitioning into control and data

This section describes how to separate an entity into control and data enti- ties. This is possible when the real channel package is used but, as explained below, this partitioning has to follow certain guidelines.

To illustrate how the partitioning is carried out, the FIFO stage in figure 8.14 in the preceding section will be separated into a latch control circuit called

latch ctrland a latch called std logic latch. The VHDL code is shown

in figure 8.19, and figure 8.20 is a graphical illustration of the partitioning that includes the unresolved signalsudanduqas explained below.

In VHDL a driver that drives a compound resolved signal has to drive all fields in the signal. Therefore a control circuit cannot drive only the acknowl- edge field in a channel. To overcome this problem a signal of the corresponding unresolved channel type has to be declared inside the partitioned entity. This is the function of the signals udanduqof type uchannel fp in figure 8.17. The control circuit then drives only the acknowledge field in this signal; this is allowed since the signal is unresolved. The rest of the fields remain unini- tialized. The unresolved signal then drives the channel; this is allowed since it drives all of the fields in the channel. The resolution function for the channel should ignore the uninitialized values that the channel is driven with. Compo- nents that use thesendandreceiveprocedures also drive those fields in the

library IEEE;

use IEEE.std_logic_1164.all; use work.real_channels.all; entity fp_latch is

port ( d : inout channel_fp; -- input data channel

q : inout channel_fp; -- output data channel

resetn : in std_logic );

end fp_latch;

architecture struct of fp_latch is component latch_ctrl

port ( rin, aout, resetn : in std_logic;

ain, rout, lt : out std_logic );

end component;

component std_logic_latch generic (width : positive);

port ( lt : in std_logic;

d : in std_logic_vector(width-1 downto 0);

q : out std_logic_vector(width-1 downto 0) );

end component; signal lt : std_logic; signal ud, uq : uchannel_fp; begin

latch_ctrl1 : latch_ctrl

port map (d.req,q.ack,resetn,ud.ack,uq.req,lt); std_logic_latch1 : std_logic_latch

generic map (width => 32) port map (lt,d.data,uq.data); d <= connect(ud);

q <= connect(uq); end struct;

Figure 8.19. Separation of the FIFO stage into an ordinary data latch and a latch control circuit.

channel that they do not control with uninitialized values. For example, an out- put to a channel drives the acknowledge field in the channel with theUvalue. The fields in a channel that are used as inputs are connected directly from the channel to the circuits that have to read those fields.

Notice in the description that the signals ud anduq do not drive d and q directly but through a function calledconnect. This function simply returns its parameter. It may seem unnecessary, but it has proved to be necessary when some of the subcircuits are described with a standard cell implementation. In a simulation a special “gate-level simulation engine” is used to simulate the

Lt d std_logic_latch q d resetn Lt Lt aout ain rin rout resetn ud q uq latch_ctl ch_in ch_out q resetn d fp_latch fp_latch _{fp_latch}

FIFO_stage FIFO_stage FIFO_stage

Figure 8.20. Separation of control and data.

standard cells [129]. During initialization it will set some of the signals to the valueX instead of to the valueUas it should. It has not been possible to get the channel resolution function to ignore theseXvalues, because the gate-level simulation engine sets some of the values in the channel. By introducing the

connect function, which is a behavioural description, the normal simulator

takes over and evaluates the channel by means of the corresponding resolution function. It should be emphasized that it is a bug in the gate-level simulation engine that necessitates the addition of theconnectfunction.

8.7.

Summary

This chapter addressed languages and CAD tools for high-level modeling and synthesis of asynchronous circuits. The text focused on a few represen- tative and influential design methods that are based languages that are similar to CSP. The reason for preferring these languages are that they support chan- nel based communication between processes (synchronous message passing) as well as concurrency at both process and statement level – two features that are important for modeling asynchronous circuits. The text also illustrated a synthesis method known as syntax directed translation. Subsequent chapters in this book will elaborate much more on these issues.

Finally the chapter illustrated how channel based communication can be implemented in VHDL, and we provided two packages containing all the nec- essary procedures and functions including: send,receiveandprobe. These packages supports a manual top-down stepwise-refinement design flow where the same test bench can be used to simulate the design throughout the entire

design process from high level specification to low level circuit implementa- tion.

This chapter on languages and CAD-tools for asynchronous design con- cludes the tutorial on asynchronous circuit design and it it time to wrap up: Chapter 2 presented the fundamental concepts and theories, and provided point- ers to the literature. Chapters 3 and 4 presented an RTL-like abstract view on asynchronous circuits (tokens flowing in static data-flow structures) that is very useful for understanding their operation and performance. This material is probably where this tutorial supplements the existing body of literature the most. Chapters 5 and 6 addressed the design of datapath operators and con- trol circuits. Focus in chapter 6 was on speed-independent circuits, but this is not the only approach. In recent years there has also been great progress in synthesizing multiple-input-change fundamental-mode circuits. Chapter 7 discussed more advanced 4-phase bundled-data protocols and circuits. Finally chapter 8 addressed languages and tools for high-level modeling and synthesis of asynchronous circuits.

The tutorial deliberately made no attempts at covering of all corners of the field – the aim was to pave a road into “the world of asynchronous design”. Now you are here at the end of the road; hopefully with enough background to carry on digging deeper into the literature, and equally importantly, with sufficient understanding of the characteristics of asynchronous circuits, that you can start designing your own circuits. And finally; asynchronous circuits do not represent an alternative to synchronous circuits. They have advantages in some areas and disadvantages in other areas and they should be seen as a supplement, and as such they add new dimensions to the solution space that the digital designer explores. Even today, many circuits can not be categorized as either synchronous or asynchronous, they contain elements of both.

The following chapters will introduce some recent industrial scale asyn- chronous chips. Additional designs are presented in [106].

Appendix: The VHDL channel packages