Details
Academic reputation Editorial positions
• C.R. Jesshope: Parallel Processing Letters, member of the Editorial Board since 1990; Special issues of IJPP on Microgrids (parts I and II), 2006, co-editor; Proc. of the IEEE Asia-Pacific Computer Systems Architecture Conference, 2006, co-editor; Proc. of the Network and Parallel Computing conference, 2007, co-editor; Special issue of Parallel Processing Letters 18(2), editor, 2008.
• A.D. Pimentel: Simulation Modelling Practice and Theory (Elsevier), member of the Editorial Board since 2007; Journal of Signal Processing Systems (Springer), member of the Editorial Board since 2008; Special issue of ACM Transactions on Embedded Computing Systems (TECS), to appear in 2009, co-editor; Special issue of Journal of Signal Processing Systems, to appear in 2009, co-editor;
Special issue of Journal of Systems Architecture, Vol. 54 (No. 11), 2008, co-editor; Special issue of Journal of Systems Architecture, Vol. 53 (No. 8), 2007, co-editor; Special issue of Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, Vol. 43 (No. 2-3), 2006, co-editor; Proc. of the IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), IEEE, 2008 and 2009, co-editor; Proc. of Systems, Architectures, MOdeling, and Simulation (SAMOS), LNCS, 2004 and 2005, co-editor.
• P.M.W. Knijnenburg (10/2005-6/2007): Special issue of Concurrency and Computation: Practice and Experience, 18(11), 2006, co-editor.
Scientific events organized
• C.R. Jesshope:General Chair, IEEE Asia-Pacific Computer Systems Architecture Conference, 2006;
Program chair, Network and Parallel Computers conference (NPC), Dalian, China, 2007; Publicity Chair, Network and Parallel Computers conference (NPC), 2004.
• A.D. Pimentel: Program Chair of the MPSoC and System Design Methods track, Design Automation and Test in Europe (DATE), 2010–; Program Chair, IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), part of the Embedded Systems Week, Grenoble, France, 2009;
Program Chair, IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), part of the Embedded Systems Week, Atlanta, USA, 2008; Program Co-Chair, EuroPar, Topic 1:
Support Tools and Environments, Delft, 2009; Local Arrangements Chair, Int. Conference on Field Programmable Logic and Applications (FPL), Amsterdam, 2007; General Chair, 5th Int. Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, 2005; Special Ses-sion Chair, IEEE 16th Int. Conference on Application-specific Systems, Architectures and Proces-sors (ASAP), Samos, Greece, 2005; Program Chair, 4th Int. Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, 2004; General and Program Chair, ASCI Win-terschool on Embedded Systems, 2004, 2006,2008, and 2010.
International functions
• C.R. Jesshope: Chairman of IFIP Working Group 10.3 Concurrent Systems (member since 1996, chair since 2006); Member IEEE Technical Committee on Parallel Processing, 1997-now; Founding Chair and Steering Committee member of the Microgrid International Workshop on on-chip concurrency, 2004-now; Member of the Steering Committee of the Asia-Pacific Computer Systems Architecture conference – ACSAC, 1996-now; Member of European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC), 2004-now.
• A.D. Pimentel: Member of the European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC), 2004–now; Co-founder and Board Member of the Int.
Symposium on Embedded Computing Systems: Architectures, Modeling, and Simulation (SAMOS), 2005–now; IEEE Senior Member since 2006; Member of IFIP Working Group 10.3 Concurrent Systems, 2009-now; Member of international PhD defense committees of Tero Kangas (TUT, Finland, 2006), Liu Yanhong (National University of Singapore, 2007).
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• C. Grelck (9/2008-): Member of the Steering Committee of the International Symposia on Implementation and Application of Functional Languages, 2004–now.
• P.M.W. Knijnenburg (10/2005-6/2007): Steering committee member of Int. Workshop on Compilers for Parallel Computers (CPC).
Invited talks
• C.R. Jesshope: Advanced Research Workshop on High Performance Computing, Cetraro, Italy, 2004; NWO SIREN Scientific ICT Research Workshop, Eindhoven, the Netherlands, 2005;
Advanced Research Workshop on High Performance Computing, Cetraro, Italy, 2006; Workshop on Software Challenges for Multicore Architectures, Tsinghua University, Beijing, China, 2006;
Dagstuhl Seminar on Programming Models for Ubiquitous Parallelism, 2007; Chinese Academy of Sciences, Institute of Computer Technology, October 2007; Chinese Academy of SPACE Sciences, Beijing Institute of Control Engineering, October 2007; Keynote to the ASCI conference, Het Heijderbos, Heijen; Panelist at Network and Parallel Computers conference (NPC), Dalian, China, 2007; Advanced Research Workshop on High Performance Computing, Cetraro, Italy, 2008;
Keynote to HPCC workshop on multi-cores, Europar Conference, Gran Canaria, Spain, 2008;
ScalPerf Workshop, Bertinoro, Italy, 2008; “Making multi-core main stream” Intel, Barcelona, 2009;
International Parallel Computing conference; Lyon, France, 2009.
• A.D. Pimentel: “Sesame: Opening Perspectives for Efficient Design Space Exploration of Embedded System Architectures”, presented at ACE Compiler Experts (Amsterdam), Synopsys, Inc., (Aachen), and Philips Research Laboratories (Eindhoven), 2003/2004; “The need for high-level modeling and simulation”, Future and Emerging Technologies meeting, 2003, Brussels, Belgium; “Sesame: Open-ing New Doors to Multi-level Design Space Exploration”. Int. Workshop on Distributed Embedded Systems, November 2005, Leiden; “Sesame: Efficient System-level Design Space Exploration”, Hi-PEAC, European network of excellence meeting, Feb. 2006, Delft; “A Framework for Exploring, Programming, and Prototyping MPSoCs”, Keynote, Progress Minisymposium on Networks on Chip, June, 2006, Leiden; “Exploring, Programming, and Prototyping MP-SoCs within 24 hours”, Key-note, 2nd HiPEAC International Workshop, Oct., 2006, Philips High Tech Campus, Eindhoven; “A Framework for Exploring, Programming, and Prototyping MPSoCs”, Tampere University of Tech-nology, Finland, October, 2006; “A Framework for Exploring, Programming, and Prototyping MPSoCs”, Keynote, Design Tools, November, 2006, Veldhoven; “Designing your favorite MP-SoC in 24 hours?”, IFIP 10.3 Concurrent Systems Working Group meeting, June, 2007, Amsterdam;
“Daedalus: A Framework for Exploring, Programming, and Prototyping MPSoCs”, Sept. 2007, Eindhoven University; “The Daedalus System-level Design Flow”, seminar at Queens University, December, 2007, Belfast, UK; “The Daedalus System-level Design Flow”, workshop at NXP Semi-conductors, Jan., 2008, Eindhoven; “Daedalus: Making System-level Design Take Off”, XOOTIC Keynote, Feb., 2008, Eindhoven; “Daedalus: Toward Composable Multimedia MP-SoC Design”, Design Automation Conference (DAC), June, 2008, Anaheim, USA; “Tool Integration and Interop-erability Challenges of a System-level Design Flow: a Case Study”, July, 2008, Int. SAMOS sympo-sium, Samos, Greece; “System-level Design Space Exploration of MP-SoCs”, Twente University of Technology, Enschede, Oct. 2008.
Program committees
• C.R. Jesshope: IFIP Int. Conference on Network and Parallel Computing (NPC), 2004-now; IEEE Asia-Pacific Computer Systems Architecture Conference, 1997-now; Int. Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation(SAMOS), 2007–now; AMWAS 2008;
HPPC 2008-now; Int. Conference on Computational Science (ICCS), 2008; HiPEAC Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, 2007; ACM International Conference on Supercomputing (ICS), 2006.
• A.D. Pimentel: IEEE International Conference of Computer Design (ICCD), 2008-now, Design Automation and Test in Europe (DATE), 2007–now, PC Chair of the MPSoC and System Design Methods track as of 2010; International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), as of 2010; Int. Conference on Field Programmable Logic and Applica-tions (FPL), 2007–now; IEEE Workshop on Embedded Systems for Real-Time Multimedia (ES-TIMedia), 2006–now; Int. Symposium on Embedded Computer Systems: Architectures, Modeling, and Simulation(SAMOS), 2001–now; Reconfigurable Architectures Workshop (RAW), 2009-now;
ACM Symposium on Applied Computing (SAC), Embedded Systems track, 2009-now; Int. Work-shop on Applied Reconfigurable Computing (ARC), 2006–now; IEEE Asia-Pacific Computer Sys-tems Architecture Conference, 2006–now; Int. Conference on Architecture of Computing Systems (ARCS), 2009-now; Int. Workshop on Reconfigurable and Multicore Embedded Systems (WoR-MES), 2009; IEEE Int. Symposium on Embedded Computing (SEC 2008), 2008; IEEE Int. Confer-ence on Embedded Software and Systems, 2008, 2009; IFIP Int. ConferConfer-ence on Embedded and Ubiquitous Computing (EUC), 2007; Int. Symposium on Embedded Multicore Systems-on-Chip (MCSoC-09), 2006-now; IFIP Int. Conference on Network and Parallel Computing (NPC), 2007, 2008; ACM International Conference on Supercomputing (ICS), 2006; Annual Simulation Sympo-sium, 2006, 2007, 2008;Int. MicroGrid Workshop, 2006 Int. Workshop on Embedded Software Op-timization (ESO), 2006, 2008; High Performance Computing & Simulation (HPCS) Conference, 2006, 2007; Int. Workshop on Parallel and Distributed Scientific and Engineering Computing, 2004.
• P.M.W. Knijnenburg (10/6/2007): ACM Int. Symposium on Applied Computing (SAC), 2005-2007; HPCC, 2006; SMART, 2006.
Full outcome list of Program CSA
2004
Academic publications
In refereed proceedings
1. M. Thompson and A. D. Pimentel, “A High-level Programming Paradigm for SystemC”, in the Proc. of the 4th Int. Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS 2004), LNCS, Samos, Greece, July, 2004.
2. C.R. Jesshope, “Scalable Instruction-level Parallelism”, In Proc. of the Int. Workshop on Computer Systems: Architectures, Modelling and Simulation (SAMOS IV), LNCS 3133, pp 383-392, July 2004.
3. C. Erbas, S. Cerav-Erbas and A. D. Pimentel, “Static Priority Scheduling of Event-Triggered Real-Time Embedded Systems”, in Proc. of the ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'04), San Diego, USA, June 23-25, 2004.
Monographs
1. A. D. Pimentel and S. Vassiliadis, editors, Proceedings of the 3rd and 4th Int. Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS 2004), LNCS 3133, Samos, Greece, July, 2004.
Awards and honors
1. A.D. Pimentel: Best paper award candidate, ACM/IEEE Int. Conference on Formal Methods and Modelsfor Codesign (MEMOCODE), 2004.
2005
Academic publications
In refereed proceedings
1. C.R. Jesshope, “Micro-grids - the exploitation of massive on-chip concurrency”, pp 203-223 (Invited paper, HPC 2004 Cetraro, June 2004), In Grid Computing: A New Frontier of High Performance Computing, 14, pp. 203-223, (ed. L. Grandinetti, Elsevier, Amsterdam, 2005).
2. K. Bousias and C.R. Jesshope, “The Challenges of Massive On-Chip Concurrency”, in Proc. of AC-SAC, Lecture Notes in Computer Science, Volume 3740, pp157 – 170, 2005.
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3. I. Bell, N. Hasasneh, and C.R. Jesshope, “Microgrids and Micro-contexts: Support Structures for Microthread Scheduling and Synchronisation”, in Proc. 1st MicroGrid Conference, Amsterdam, July 2005
4. A. D. Pimentel, “A Case for Visualization-integrated System-level Design Space Exploration”, in the Proc. of the 5th Int. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS 2005), pp. 455-464, LNCS, Samos, Greece, July, 2005.
Monographs
1. T. D. Hämäläinen, A. D. Pimentel, J. Takala, and S. Vassiliadis, editors, Proceedings of the 5th Int.
Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS 2005), LNCS 3553, Samos, Greece, July, 2005.
2006
Academic publications
In refereed journals
1. Bell, I., Hasasneh, N., and Jesshope, C. R., “Supporting Microthread Scheduling and Synchronisa-tion in CMPs”. InternaSynchronisa-tional Journal of Parallel Programming, 34(4), 343-381, 2006.
2. Jesshope, C. R., “Microthreading, a Model for Distributed Instruction-level Concurrency”. Parallel Processing Letters, 16(2), 209-228, 2006.
3. K. Bousias, N.M. Hasasneh and C.R. Jesshope, “Instruction-level parallelism through microthread-ing - a scalable Approach to chip multiprocessors”, The Computer Journal, Vol. 49 (No. 3), May 2006.
4. A.D. Pimentel, C. Erbas, and S. Polstra, “A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels”, in IEEE Transactions on Computers, pp. 99-112, Vol.
55 (No. 2), Feb. 2006.
5. C. Erbas, S. Cerav-Erbas, and A.D. Pimentel, “Multiobjective Optimization and Evolutionary Algo-rithms for the Application Mapping Problem in Multiprocessor System-on-Chip Design”. IEEE Transactions on Evolutionary Computation, 10(3), 358-374, 2006.
6. F.J. Cazorla, P.M.W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramirez, and M. Valero, “Pre-dictable Performance in SMT processors: Synergy Between the OS and SMTs”. IEEE Transactions on Computers, 55(7), 785-799, 2006.
7. K. Heydeman, F. Bodin, P.M.W. Knijnenburg, and L. Morin, “UFS: a Global Trade-off Strategy for Loop Unrolling for VLIW Architectures”. Concurrency and Computation: Practice and Experience, 18(11), 1413-1434, 2006.
In refereed proceedings
1. T. Bernard, K. Bousias, B. de Geus, M. Lankamp, L. Zhang, A.D. Pimentel, P.M.W. Knijnenburg, and C.R. Jesshope, “A Microthreaded Architecture and its Compiler”. In Proc. of the Int. Workshop on Compilers for Parallel Computers (pp. 326-340), 2006.
2. M. Haneda, P.M.W. Knijnenburg, H.A.G. Wijshoff, “Code Size Reduction by Compiler Tuning”. In Proc. of the Int. Workshop on Embedded Computer Systems: Architectures, Modeling, and Simula-tion (SAMOS), 2006.
3. M. Haneda, P.M.W. Knijnenburg, and H.A.G. Wijshoff, “On the Impact of Data Input Sets on Statis-tical Compiler Tuning”. In Proc. of the Workshop on Performance Optimization of High-Level Lan-guages and Libraries (POHLL), 2006.
4. N. Hasasneh, I. Bell, and C.R. Jesshope, “Scalable and Partitionable Asynchronous Arbiter for Mi-cro-threaded Chip Multiprocessors”. In Proc. of Architecture of Computing Systems (ARCS 2006) (pp. 252-267), 2006.
5. C.R. Jesshope, “µTC: an intermediate language for programming chip multiprocessors”. In Proc. of the Asia-Pacific Computer Systems Architecture Conference, 2006.
6. A.D. Pimentel, M. Thompson, S. Polstra, and C. Erbas, “On the Calibration of Abstract Performance Models for System-level Design Space Exploration”. In Proc. of the Int. Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (IC-SAMOS 2006) (pp. 71-77), 2006.
7. M. Thompson, A.D. Pimentel, S. Polstra, and C. Erbas, “A Mixed-level Co-simulation Method for System-level Design Space Exploration”. In Proc. of the IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia'06) (pp. 27-32), 2006.
8. T. E. Pronk, S. Polstra, A. D. Pimentel, M. Roos, T. M. Breit, “Evaluating the Design of Biological Cells Using a Computer Workbench”, in Proc. of the 5th European Conference on Computational Biology, Eilat, Israel, Sept. 2006.
Monographs
1. Jesshope, C. R., and Shafarenko, A. (Eds.). Int. Journal of Parallel Programming, 34(3), 2006.
2. Jesshope, C. R., and Shafarenko, A. (Eds.). Int. Journal of Parallel Programming, 34(4), 2006.
3. Pimentel, A.D. and Vassiliadis, S., editors, Special Issue of the Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, Vol. 43 (No. 2-3), May 2006.
4. Knijnenburg, P. M. W. (Ed.). (2006). Concurrency and Computation: Practice and Experience (18, 11). UK: John Wiley & Sons, Ltd.
PhD Thesis
1. C. Erbas, November 2006, “System-Level Modeling and Design Space Exploration for Multiproces-sor Embedded System-on-Chip Architectures”, PhD thesis, Department of Computer Science, Uni-versity of Amsterdam. Amsterdam UniUni-versity Press, The Netherlands. ISBN: 90-5629-455-5.
2007
Academic publications In refereed journals
1. C. Erbas, A. D. Pimentel, M. Thompson, and S. Polstra, “A Framework for System-level Modeling and Simulation of Embedded Systems Architectures”, in EURASIP Journal on Embedded Systems, 2007, available online: DOI 10.1155/2007/82123.
2. T. E. Pronk, A. D. Pimentel, M. Roos, T. M. Breit, “Taking the Example of Computer Systems En-gineering for the Analysis of Biological Cell Systems”, in BioSystems, pp. 623-635, Vol. 90 (No. 3), Nov./Dec. 2007.
3. C. Erbas, S. Cerav-Erbas and A. D. Pimentel, “Static Priority Scheduling of Event-Triggered Real-Time Embedded Systems'” in Int. Journal on Formal Methods for System Design, pp. 29-47, Vol. 30 (No. 1), Feb. 2007, Springer. (selected from the 3 best papers of ACM/IEEE MEMOCODE '04).
4. I. Bell, N. M. Hasasneh and C. R. Jesshope, “Asynchronous arbiter for micro-threaded Chip multi-processors”, in Journal of Systems Architecture, pp. 253-262, 53(5-6), 2007.
In refereed proceedings
1. P. van Stralen and A. D. Pimentel, “Signature-based Microprocessor Power Modeling for Rapid Sys-tem-level Design Space Exploration”, in the Proc. of the IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia '07), pp. 33-40, Salzburg, Austria, Oct., 2007.
2. M. Thompson, T. Stefanov, H. Nikolov, A. D. Pimentel, C. Erbas, S. Polstra, and E. F. Deprettere,
“A Framework for Rapid System-level Exploration, Synthesis, and Programming of Multimedia MP-SoCs”, in the Proc. of the ACM/IEEE/IFIP Int. Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS '07), pp. 9-14, Salzburg, Austria, Oct., 2007.
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3. M. Thompson and A. D. Pimentel, “Towards Multi-application Workload Modeling in Sesame for System-level Design Space Exploration”, in the Proc. of the 7th Int. Workshop on Embedded Com-puter Systems: Architectures, MOdeling, and Simulation (SAMOS '07), pp. 222-232, LNCS, Samos, Greece, July, 2007.
4. T. E. Pronk, S. Polstra, A. D. Pimentel, and T. Breit, “Evaluating the Design of Biological Cells us-ing a Computer Workbench”, in the Proc. of the 40th Annual Simulation Symposium, pp. 88-98, IEEE Computer Society Press, Norfolk, USA, March, 2007.
5. T.A.M. Bernard, C.R. Jesshope and P.M.W. Knijnenburg, “Strategies for Compiling μTC to Novel Chip Multiprocessors”, in the Proc. of the Int. Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS 2007), pp. 127-138, 2007.
6. L. Zhang and C. Jesshope, “On-Chip COMA Cache-coherence Protocol for Microgrids of Mi-crothreaded Cores”, Eds. Bouge et. al., Proc EuroPar 2007 Workshops, LNCS Volume 4854, Sprin-ger, pp 38-48, 2007.
7. L. Zhang and C. Jesshope, “On-Chip COMA Cache Hierarchy for Microthreaded Architecture”, in the Proceedings of the 13th Annual Conference of the Advanced School for Computing and Imaging (ASCI), 2007.
8. T.D Vu and C. R. Jesshope, “Formalizing SANE virtual processor in thread algebra,” in M. Butler, M. G. Hinchley and M. M. Larrondo-Petrie, eds. ICFEM 2007, pp 345-365, 2007.
9. N. M. Hasasneh, I. Bell and C. R. Jesshope, “High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids”, in the Proc. Computer Systems and Applications (AICCSA '07), pp. 301-308, 2007.
10. S. van Haastregt, P.M.W. Knijnenburg, “Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search”. in the Proc. of the De-sign, Automation and Test in Europe Conference (DATE), 2007: 606-611
11. F.J. Cazorla, E. Fernández, P.M.W. Knijnenburg, A. Ramírez, R. Sakellariou, M. Valero, “On the Problem of Minimizing Workload Execution Time in SMT Processors”. ”, in the Proc. of the Int.
Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS 2007), 2007: 66-73
Monographs
1 J. Takala, T.D. Hämäläinen, A.D. Pimentel and S. Vassiliadis (Eds.), Journal of Systems Architec-ture, 53(8), Aug., 2007.
2 H. Blume, G. Gaydadjiev, J. Glossner, P.M.W. Knijnenburg: Proceedings of 2007 International Con-ference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007 IEEE 2007
2008
Academic publications In refereed journals
1. C. R. Jesshope, “Operating Systems in Silicon and the Dynamic Management of Resources in Many-core Chips”, in Parallel Processing Letters (PPL), pp. 257-274, Vol. 18 (No. 2), 2008.
2. K. Bousias, L. Guang, C.R. Jesshope and M. Lankamp, “Implementation and evaluation of a mi-crothread architecture”, in the Journal of Systems Architecture, 2008, DOI 10.1016/j.sysarc.
2008.07.001.
3. A. D. Pimentel, “The Artemis Workbench for System-level Performance Evaluation of Embedded Systems”, in Int. Journal of Embedded Systems, pp. 181-196, Vol. 3 (No. 3), 2008.
4. A. D. Pimentel, M. Thompson, S. Polstra and C. Erbas, “Calibration of Abstract Performance Mod-els for System-level Design Space Exploration”, in Journal of Signal Processing Systems, pp. 99-114, Vol. 50 (No. 2), Feb. 2008, Springer.
5. T. E. Pronk, S. Polstra, A. D. Pimentel, and T. M. Breit, “Towards Design Space Exploration for Biological Systems”, in the Journal of Computers (invited paper), pp. 1-9, Vol. 3 (No. 2), Feb. 2008.
6. P. van Stralen and A. D. Pimentel, “A High-level Microprocessor Power Modeling Technique based on Event Signatures”, in the Journal of Signal Processing Systems, Springer, available online DOI 10.1007/s11265-008-0301-8 in 2008.
In refereed proceedings
1. L. Zhang and C.R. Jesshope, “On-Chip COMA Cache-Coherence Protocol for Microgrids of Mi-crothreaded Cores”, in the Proc. of Euro-Par 2007 Workshops: Parallel Processing, pp. 38-48, March, 2008.
2. T. Duong Vu, L. Zhang and C.R. Jesshope, “The Verification of the On-Chip COMA Cache Coher-ence Protocol”, in the Proc. of Algebraic Methodology and Software Technology, pp. 413-429, July, 2008.
3. C. R. Jesshope, J-M. Philippe and M. van Tol, “An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency”, in the Proc. of the Intl. Symposium on Systems, Architectures, Modeling and Simulation (SAMOS-2008), pp. 218-228, July, 2008.
4. T. Bernard, K. Bousias, L. Guang, C. R. Jesshope, M. Lankamp, M. W. van Tol and L. Zhang, “A General Model of Concurrency and its Implementation as Many-Core Dynamic RISC Processors”, in the Proc. of Intl. Symposium on Systems, Architectures, Modeling and Simulation (SAMOS-2008), pp. 1-9, July, 2008.
5. C. R. Jesshope, “A Model for the Design and Programming of Multi-cores”, in the Proc. of Ad-vances in Parallel Computing, 16, High performance Computing and Grids in Action, pp. 37-55, 2008.
6. H. Nikolov, M. Thompson, T. Stefanov, A. D. Pimentel, S. Polstra, R. Bose, C. Zissulescu, and E. F.
Deprettere, ”Daedalus: Toward Composable Multimedia MP-SoC Design”, invited paper, in the Proc. of the ACM/IEEE Int. Design Automation Conference (DAC '08), pp. 574-579, Anaheim, USA, June, 2008.
7. K. Sigdel, M. Thompson, A. D. Pimentel, T. Stefanov, and K. Bertels, ”System Level Design Space Exploration of Dynamic Reconfigurable Architectures”, in the Proc. of Int. Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS '08), pp. 279-288, LNCS, Samos, Greece, July, 2008.
8. S. Jaddoe and A. D. Pimentel, ”Signature-based Calibration of Analytical System-level Performance Models”, in the Proc. of Int. Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS '08), pp. 268-278, LNCS, Samos, Greece, July, 2008.
9. A. D. Pimentel, T. Stefanov, H. Nikolov, M. Thompson, S. Polstra and E. F. Deprettere, “Tool Inte-gration and Interoperability Challenges of a System-level Design Flow: a Case Study”, invited paper, in the Proc. of Int. Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS '08), pp. 167-176, LNCS, Samos, Greece, July, 2008.
10. K. Sigdel, M. Thompson, A. D. Pimentel, and K.L.M. Bertels, ”Towards System Level Runtime De-sign Space Exploration of Reconfigurable Architecture”, in the Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC08), Veldhoven, The Netherlands, November 2008.
Monographs
1. C.R. Jesshope and A. Shafarenko, editors, Concurrency engineering, Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference (ACSAC), 2008.
2. M. Berekovic, T. D. Hämäläinen, and A.D. Pimentel, editors, Special Issue of the Journal of Systems Architecture, Vol. 54 (No. 11), pp. 1017-1018, 2008.
3. P. Eles and A.D. Pimentel, editors, Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia '08), Atlanta, USA, October, 2008.
Professional publications and products
1. A.D. Pimentel and D. Schipper, “Technisch Lego met een Duplo Interface”, Bits & Chips, February,
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2008, pp. 38-39, http://www.bits-chips.nl/nieuws/achtergrond/bekijk/artikel/technisch-lego-met-een-duplo-interface.html
Other results Software
1. During the period 2004-2008, the CSA group invested significant time and effort in the development of the Sesame system-level simulation and design space exploration framework. The Sesame frame-work has gained a prominent position in the domain of early system-level design space exploration and is used in various academic and industrial groups from all over the world. Moreover, the interest in Sesame is still steadily growing, demonstrated by the emails we receive from new (potential) us-ers. Recently, Sesame has been integrated in the Daedalus design flow for system-level design of MultiProcessor Systems-on-a-Chip. See http://daedalus.liacs.nl/ for the (open source) software. In-terest in Daedalus is taking off very rapidly: companies like Chess B.V. and ST Micro are e.g.
known users of this software.
2. Within the scope of CSA’s DRISC core and Microgrid work, an entire compiler tool-chain as well as a number of different simulators (a cycle accurate DRISC microgrid simulator, a high-level Micro-grid simulator, a COMA-based memory hierarchy simulator, etc.) have been developed. See http://www.apple-core.info/ for the software.