IA-64 Execution Environment
3.1.8 Application Registers
The application register file includes special-purpose data registers and control registers for application-visible processor functions for both the IA-32 and IA-64 instruction sets. These registers can be accessed by IA-64 application software (except where noted). Table 3-3 contains a list of the application registers.
Table 3-3. Application Registers
Register Name Description Execution Unit Type
AR 0-7 KR 0-7a
a. Writes to these registers when the privilege level is not zero result in a Privileged Register fault. Reads are always allowed.
Kernel Registers 0-7 M
AR 8-15 Reserved
AR 16 RSC Register Stack Configuration Register AR 17 BSP Backing Store Pointer (read-only) AR 18 BSPSTORE Backing Store Pointer for Memory Stores
AR 19 RNAT RSE NaT Collection Register
AR 20 Reserved
AR 21 FCR IA-32 Floating-point Control Register
AR 22 – AR 23 Reserved
AR 24 EFLAGb
b. Some IA-32 EFLAG field writes are silently ignored if the privilege level is not zero. See Section 10.3.2 for details.
IA-32 EFLAG register
AR 25 CSD IA-32 Code Segment Descriptor
AR 26 SSD IA-32 Stack Segment Descriptor
AR 27 CFLGa IA-32 Combined CR0 and CR4 register AR 28 FSR IA-32 Floating-point Status Register AR 29 FIR IA-32 Floating-point Instruction Register AR 30 FDR IA-32 Floating-point Data Register
AR 31 Reserved
AR 32 CCV Compare and Exchange Compare Value Register
AR 33 – AR 35 Reserved
AR 36 UNAT User NaT Collection Register
AR 37 – AR 39 Reserved
AR 40 FPSR Floating-point Status Register
AR 41 – AR 43 Reserved
AR 44 ITC Interval Time Counter
AR 45 – AR 47 Reserved
AR 48 – AR 63 Ignored M or I
AR 64 PFS Previous Function State I
AR 65 LC Loop Count Register
AR 66 EC Epilog Count Register
AR 67 – AR 111 Reserved AR 112 – AR 127 Ignored M or I
Application registers can only be accessed by either a M or I execution unit. This is specified in the last column of the table. The ignored registers are for future backward-compatible extensions.
3.1.8.1
Kernel Registers (KR 0-7 – AR 0-7)
Eight user-visible IA-64 64-bit data kernel registers are provided to convey information from the operating system to the application. These registers can be read at any privilege level but are writable only at the most privileged level. KR0 - KR2 are also used to hold additional IA-32 register state when the IA-32 instruction set is executing. See “Instruction Set Transitions” on page 10-1 of Volume 2 for register details when calling IA-32 code.
3.1.8.2
Register Stack Configuration Register (RSC – AR 16)
The Register Stack Configuration (RSC) Register is a 64-bit register used to control the operation of the IA-64 Register Stack Engine (RSE). The RSC format is shown in Figure 3-3 and the field description is contained in Table 3-4. Instructions that modify the RSC can never set the privilege level field to a more privileged level than the currently executing process.
3.1.8.3
RSE Backing Store Pointer (BSP – AR 17)
The RSE Backing Store Pointer is a 64-bit read-only register (Figure 3-4). It holds the address of the location in memory which is the save location for GR 32 in the current stack frame. See “RSE and Backing Store Overview” on page 6-1 of Volume 2.
Figure 3-3. RSC Format
63 30 29 16 15 5 4 3 2 1 0
rv loadrs rv be pl mode
34 14 11 1 2 2
Table 3-4. RSC Field Description
Field Bit Range Description
mode 1:0 RSE mode – controls how aggressively the RSE saves and restores register frames. Eager and intensive settings are hints and can be implemented as lazy. Bit Pattern RSE Mode Bit 1:
eager loads
Bit 0: eager stores
00 enforced lazy disabled disabled
10 load intensive enabled disabled
01 store intensive disabled enabled
11 eager enabled enabled
pl 3:2 RSE privilege level – loads and stores issued by the RSE are at this privilege level
be 4 RSE endian mode – loads and stores issued by the RSE use this byte ordering (0: little endian; 1: big endian)
loadrs 29:16 RSE load distance to tear point – value used in the loadrs instruction for synchronizing the RSE to a tear point
3.1.8.4
RSE Backing Store Pointer for Memory Stores (BSPSTORE – AR 18)
The RSE Backing Store Pointer for memory stores is a 64-bit register (Figure 3-5). It holds the address of the location in memory to which the RSE will spill the next value. See “RSE and Backing Store Overview” on page 6-1 of Volume 2.
3.1.8.5
RSE NaT Collection Register (RNAT – AR 19)
The RSE NaT Collection Register is a 64-bit register (Figure 3-6) used by the RSE to temporarily hold NaT bits when it is spilling general registers. Bit 63 always reads as zero and ignores all writes. See “RSE and Backing Store Overview” on page 6-1 of Volume 2.
3.1.8.6
Compare and Exchange Value Register (CCV – AR 32)
The Compare and Exchange Value Register is a 64-bit register that contains the compare value used as the third source operand in the IA-64 cmpxchg instruction.
3.1.8.7
User NaT Collection Register (UNAT – AR 36)
The User NaT Collection Register is a 64-bit register used to temporarily hold NaT bits when saving and restoring general registers with the IA-64 ld8.fill and st8.spill instructions.
3.1.8.8
Floating-point Status Register (FPSR – AR 40)
The floating-point status register (FPSR) controls traps, rounding mode, precision control, flags, and other control bits for IA-64 floating-point instructions. FPSR does not control or reflect the status of IA-32 floating-point instructions. For more details on the FPSR, see “Floating-point Status Register” on page 5-4.
Figure 3-4. BSP Register Format
63 3 2 1 0
pointer 0
61 3
Figure 3-5. BSPSTORE Register Format
63 3 2 1 0
pointer ig
61 3
Figure 3-6. RNAT Register Format
63 0
ig RSE NaT Collection
3.1.8.9
Interval Time Counter (ITC – AR 44)
The Interval Time Counter (ITC) is a 64-bit register which counts up at a fixed relationship to the processor clock frequency. Applications can directly sample the ITC for time-based calculations and performance measurements. System software can secure the interval time counter from non- privileged IA-64 access. When secured, a read of the ITC at any privilege level other than the most privileged causes a Privileged Register fault. The ITC can be written only at the most privileged level. The IA-32 Time Stamp Counter (TSC) is equivalent to ITC. ITC can directly be read by the IA-32 rdtsc (read time stamp counter) instruction. System software can secure the ITC from non- privileged IA-32 access. When secured, an IA-32 read of the ITC at any privilege level other than the most privileged raises an IA-32_Exception(GPfault).
3.1.8.10
Previous Function State (PFS – AR 64)
The IA-64 Previous Function State register (PFS) contains multiple fields: Previous Frame Marker (pfm), Previous Epilog Count (pec), and Previous Privilege Level (ppl). Figure 3-7 diagrams the PFS format and Table 3-5 describes the PFS fields. These values are copied automatically on a call from the CFM register, Epilog Count Register (EC), and PSR.cpl (Current Privilege Level in the Processor Status Register) to accelerate procedure calling.
When an IA-64 br.call or brl.call is executed, the CFM, EC, and PSR.cpl are copied to the PFS and the old contents of the PFS are discarded. When an IA-64 br.ret is executed, the PFS is copied to the CFM and EC. PFS.ppl is copied to PSR.cpl, unless this action would increase the privilege level. For more details on the PSR see Vol2, Section 3.3.2.
The PFS.pfm has the same layout as the CFM (see Section 3.1.7), and the PFS.pec has the same layout as the EC (see Section 3.1.8.12).
3.1.8.11
Loop Count Register (LC – AR 65)
The Loop Count register (LC) is a 64-bit register used in IA-64 counted loops. LC is decremented by counted-loop-type branches.
Figure 3-7. PFS Format
63 62 61 58 57 52 51 38 37 0
ppl rv pec rv pfm
2 4 6 14 38
Table 3-5. PFS Field Description
Field Bit Range Description
pfm 37:0 Previous Frame Marker
pec 57:52 Previous Epilog Count
ppl 63:62 Previous Privilege Level
3.1.8.12
Epilog Count Register (EC – AR 66)
The Epilog Count register (EC) is a 6-bit register used for counting the final (epilog) stages in IA- 64 modulo-scheduled loops. See “Modulo-scheduled Loop Support” on page 4-27 A diagram of the EC register is shown in Figure 3-8.
3.1.9
Performance Monitor Data Registers (PMD)
A set of performance monitoring registers can be configured by privileged software to be
accessible at all privilege levels. Performance monitor data can be directly sampled from within the application. The operating system is allowed to secure user-configured performance monitors. Secured performance counters return zeros when read, regardless of the current privilege level. The performance monitors can only be written at the most privileged level. Refer to Chapter 7 of
Volume 2 for details. Performance monitors can be used to gather performance information for both IA-32 and IA-64 instruction set execution.
3.1.10
User Mask (UM)
The user mask is a subset of the Processor Status Register and is accessible to IA-64 application programs. The user mask controls memory access alignment, byte-ordering and user-configured performance monitors. It also records the modification state of IA-64 floating-point registers.
Figure 3-9 show the user mask format and Table 3-6 describes the user mask fields. For more details on the PSR refer to “Processor Status Register (PSR)” on page 3-6 in Volume 2.
Figure 3-8. Epilog Count Register Format
63 6 5 0
ig epilog count
58 6
Figure 3-9. User Mask Format
5 4 3 2 1 0
mfh mfl ac up be rv
1 1 1 1 1 1
Table 3-6. User Mask Field Descriptions
Field Bit Range Description
rv 0 Reserved
be 1 IA-64 Big-endian memory access enable
(controls loads and stores but not RSE memory accesses) 0: accesses are done little-endian
1: accesses are done big-endian
This bit is ignored for IA-32 data memory accesses. IA-32 data references are always performed little-endian.
up 2 User performance monitor enable for IA-32 and IA-64 instruction set execution 0: user performance monitors are disabled
1: user performance monitors are enabled
ac 3 Alignment check for IA-32 and IA-64 data memory references
0: unaligned data memory references may cause an Unaligned Data Reference fault. 1: all unaligned data memory references cause an Unaligned Data Reference fault.