Control Speculation and Compares

As stated earlier, most instructions that write a register file other than the general registers or the floating-point registers are non-speculative. The compare (cmp, cmp4, fcmp), test bit (tbit), floating-point class (fclass), and floating-point approximation (frcpa, frsqrta) instructions are special cases. These instructions read general or floating-point registers and write one or two predicate registers.

For these instructions, if any source contains a deferred exception token, all predicate targets are either cleared or left unchanged, depending on the compare type (see Table 4-10 on page 4-9). Software can use this behavior to ensure that any dependent conditional branches are not taken and any dependent predicated instructions are nullified. See “Predication” on page 4-7.

Deferred exception tokens can also be tested for with certain compare instructions. The test NaT (tnat) instruction tests the NaT bit corresponding to the specified general register and writes two predicate results. The floating-point class (fclass) instruction can be used to test for a NaTVal in a floating-point register and write the result to two predicate registers. (fclass does not clear both predicate targets in the presence of a NaTVal input if NaTVal is one of the classes being tested for.)

4.4.4.4

Control Speculation without Recovery

A non-speculative instruction that reads a register containing a deferred exception token will raise a Register NaT Consumption fault. Such instructions can be thought of as performing a non- recoverable speculation check operation. In some compilation environments, it may be true that the only exceptions that are deferred are fatal errors. In such a program, if the result of a speculative calculation is checked and a deferred exception token is found, execution of the program is terminated. For such a program, the results of speculative calculations can be checked simply by using non-speculative instructions.

4.4.4.5

Operating System Control over Exception Deferral

An additional mechanism is defined that allows the operating system to control the exception behavior of speculative loads. The operating system has the option to select which exceptions are deferred automatically in hardware and which exceptions will be handled (and possibly deferred) by software. See “Deferral of IA-64 Speculative Load Faults” on page 5-10 of Volume 2.

4.4.4.6

Register Spill and Fill

Special store and load instructions are provided for spilling a register to memory and preserving any deferred exception token, and for restoring a spilled register.

The spill and fill general register instructions (st8.spill, ld8.fill) are defined to save/restore a general register along with the corresponding NaT bit.

The st8.spill instruction writes a general register’s NaT bit into the User NaT Collection application register (UNAT), and, if the NaT bit was 0, writes the register’s 64-bit data portion to memory. If the register’s NaT bit was 1, the UNAT is updated, but the memory update is

implementation specific, and must consistently follow one of three spill behaviors: 1. The st8.spill may not update memory with the register’s 64-bit data portion, or 2. The st8.spill may write a zero to the specified memory location, or

3. The st8.spill may write the‘ register’s 64-bit data portion to memory, only if that implementation returns a zero into the target register of all NaTed speculative loads, and that implementation also guarantees that all NaT propagating instructions perform all

computations as specified by the instruction pages.

Bits 8:3 of the memory address determine which bit in the UNAT register is written.

The ld8.fill instruction loads a general register from memory taking the corresponding NaT bit from the bit in the UNAT register addressed by bits 8:3 of the memory address. The UNAT register must be saved and restored by software. It is the responsibility of software to ensure that the contents of the UNAT register are correct while executing st8.spill and ld8.fill instructions. The floating-point spill and fill instructions (stf.spill, ldf.fill) are defined to save/restore a floating-point register (saved as 16 bytes) without surfacing an exception if the FR contains a NaTVal (these instructions do not affect the UNAT register).

The general and floating-point spill/fill instructions allow spilling/filling of registers that are targets of a speculative instruction and may therefore contain a deferred exception token. Note also that transfers between the general and floating-point register files cause a conversion between the two deferred exception token formats.

Table 4-14 lists the state relating to control speculation. Table 4-15 summarizes the instructions related to control speculation.

4.4.5

Data Speculation

Just as control speculative loads and checks allow the compiler to schedule instructions across control dependencies, data speculative loads and checks allow the compiler to schedule instructions across some types of ambiguous data dependencies. This section details the usage model and semantics of data speculation and related instructions.

Table 4-14. State Related to Control Speculation

Register Description

NaT bits 65th bit associated with each GR indicating a deferred exception NaTVal Pseudo-Zero encoding for FR indicating a deferred exception UNAT User NaT collection application register

Table 4-15. Instructions Related to Control Speculation

Mnemonic Operation

ld.s, ldf.s, ldfp.s GR and FR speculative loads ld8.fill, ldf.fill Fill GR with NaT collection, fill FR st8.spill, stf.spill Spill GR with NaT collection, spill FR

chk.s Test GR or FR for deferred exception token