Asynchronous Pipelines

In a pipelined asynchronous system, parts of the circuit synchronize locally using a request- acknowledge handshake protocol. These handshakes control the flow of data into and out of registers, which are usually implemented as latches. A pipeline operates correctly if the handshaking protocol prevents data from being lost or overwritten while still allowing for the flow of data between stages.

Figure2.1shows the basic structure of a self-timed pipeline. Each pipeline stage consists of a controller, a storage element (“data latch”), and processing logic. Typically, a stage generates a requestto initiate a handshake with its successor stage, indicating that new data is ready. If the successor stage is empty it accepts the data and performs two further actions: (i) it acknowledges its predecessor for the data received and, (ii) initiates a similar handshake with its own successor stage. Many variations on this basic protocol have been developed, and a variety of asynchronous pipeline controller implementations exist.

2.1.1

Data Encodings within Asynchronous Pipelines

Pipeline styles can also be categorized based on the data encoding employed. Using data encodings to improve robustness or reduce energy consumption is an active area of research

Figure 2.1: A simple self-timed pipeline

[38,34], so this section will not provide a full description of possible data encodings. Instead, it will give some idea of the main types of data encodings used.

Bundled Data

A simple yet effective approach is the bundled data encoding, which is also known as single- rail. Each data bit is represented by exactly one wire, with one additional wire for the request bit. While the data bits are processed by a block of logic within the stage, the request bit must go through some matched delay—a set of gates that slows the outgoing request so it stays coherent in time with the data. This style is simple and practical, but it does not take advantage of function blocks that have variable delays.

Dual-Rail Encoding

Dual-rail data encoding uses two wires per data bit, so that the request signal is essentially built in to the encoding. Table 2.1 shows one possible dual-rail representation that encodes both the value of the data and the presence of new data.

This encoding scheme allows the stage to indicate completion as soon as it is finished, though detecting this completion can add extra overhead.

Table 2.1: Dual rail data encoding. Dual-rail code

0 0 data not ready

0 1 0 request

1 0 1 request

1 1 unused

2.1.2

Asynchronous Handshaking Protocols

two-phase Protocols

Two phase protocols have handshaking cycles that are made up of two events. Specifically, the value of the request changes once and then the value of the acknowledge changes once to complete the handshake. As a result, 2-phase protocols use transition based encodings: a transition on a line rather than the value of the line indicates an event.

four-phase Protocols

Four phase protocols have handshaking cycles that are made up for four events. Typically, the request goes high and the acknowledge goes high as a response. Then the request goes low to a reset value, and the acknowledge also resets to a low value. This protocol has more events than a two-phase protocol, but the logic implementations are often simpler, because level-based logic is a simpler design style than transition-based logic.

2.1.3

Asynchronous Pipeline Styles

Many different implementations for asynchronous pipelines have been developed, which use different combinations of data encodings and handshaking protocols. [61, 15, 42, 59, 55, 72, 67] In this dissertation, I use the following four circuit styles as examples whenever the circuit-level details of a pipeline stage need to be demonstrated.

!"

req

ack

ack

req

data

data

Figure 2.2: Sutherland’s Micropipeline with Muller C-element.

Sutherland’s Micropipelines

Suterland’s Micropipeline style [61] is a two-phase controller that uses bundled data. As shown in Figure2.2, it uses the Muller C-element [40] as the control circuit. Since the output of the C-element to the latch uses transition signaling, the latch is a special transition sensitive latch. When the pipeline line is in operation, every transition on the request wire—either high to low or low to high—indicates that a new data is available. The next stage will send back a corresponding acknowledge signal when it has finished processing the previous data.

MOUSETRAP Pipelines

MOUSETRAP _{[55], shown in Figure2.3, is a two-phase pipeline style that uses static logic.} Since MOUSETRAP_{uses transition signaling for the requests and acknowledges, every tran-} sition on a request wire indicates new data is ready and every transition on an acknowledge wire indicates that old data can be overwritten. Thus, when the request and acknowledge go- ing into a stage are the same, the stage becomes “empty” and when they are different the stage becomes “full”. The latches that hold data begin transparent and become opaque just after new data arrives. The latches themselves do not use transition signaling, since thexnoracts

req

ack

ack

req

data

_data

Figure 2.3: TheMOUSETRAPpipeline style.

as a transition to level converter.

GasP Pipelines

GasP _{[59] is a four-phase pipeline style that uses static logic. The data latches in a} GasP pipeline begin closed, and must open and then close again upon receiving each new data item. The most distinctive feature ofGasP_{is that a single wire, called the state conductor, is used} to transmitboththe request and acknowledge signals between a pair of adjacent stages. A low signal on the state conductor wire indicates that the previous stage is“full” and a high signal indicates that it is “empty”.

The controller for GasP_{is a self resettingNAND, as shown in Figure 2.4. When both of} the inputs to theNANDgo high, it goes low. After some delay, this low transition triggers the NANDto reset back to high. Specifically, two possible reset paths, r1 andr2, can cause the NANDto go high again. Pathr1consists of one pull up transistor and one inverter (inva). Path

r2 consists of one inverter (invb) and one pull down transistor. The time, treset, to reset the NANDis thesmallerof the two times:treset =min(tpull up+tINVa↓, tINVb↑+tpull down).

req_N-1

req_N

ack_N ack_N-1

data_N-1 data_N

Figure 2.4: The GasP pipeline style.

High-Capacity Pipelines

The high-capacity (HC_{) pipeline [54] is a four-phase pipeline style that uses dynamic logic.} It islatchless. Instead, the dynamic logic of each stage has an “isolate phase”, in which its output is protected from further input changes. Specifically, during the isolate phase, the logic is neither precharging nor evaluating.

AnHC_{pipeline stage simply cycles through three phases. After it completes its evaluate} phase, it enters its isolate phase and subsequently its precharge phase. As soon as precharge is complete, it re-enters the evaluate phase again, completing the cycle.