Basic Structure and Principles of IGBT

Fig. 2.10 shows the basic structure of IGBT. It looks like a MOSFET with a p-type Si base added in the bottom. This structure appears that it could never conduct current from

N+ N+ P+ N- drift region N+ buffer layer P Collector Emitter Gate SiO2 SiO2 Accumulation layer Channel Electrons flow through

MOS-channel to drift region Holes flow under channel to emitter

Depletion layer due to reverse biased PN junction

Hole injection

Figure 2.10: Basic IGBT structure and its behavior in the on-state.

collector to emitter since N-P+ junction will be reverse biased if the collector-emitter voltage

VCE is positive. However, the special gate design makes it possible to control its conductivity.

The gate terminal is isolated by a oxide layer and is placed on the top of the P-well. This structure can be thought of as a capacitor, termed gate oxide capacitance COX. When

a small positive gate-emitter voltageVGE is applied, the positive charge induced on the gate

terminal requires the same amount of negative charge on the Si side. The electric field of the positive charge pushes the holes away from the Si-oxide interface hence forms a depletion layer. Further increase VGE, the depletion layer starts to expand in thickness and starts

to attract free electrons to provide the required negative charge. When VGE increased to a

certain level, the density of free electrons at the interface will become high enough to form a layer which is highly conductive, as shown in Fig. 2.10. Such value of VGE is termed the

channel.

When VGE > VT H, the IGBT is turned on and able to forward conduct. The electrons

flow through the MOS channel into the drift region and cause the same amount of holes to be injected from the collector into the drift region, as indicated in Fig. 2.10. This double injection will lead to conductivity modulation and reduce the on-state voltage drop (VCE)

just as it does in the diode. The injected holes move cross the drift region by both diffusion and drift. When they enters the P-well, their space charge will attract electrons from the emitter terminal hence the excess holes are quickly recombined. While the injected electrons move towards the opposite direction and enter the p-type collector region where they either recombine with the majority carriers or move into the collector metallisation.

When VGE < VT H, the charge of gate oxide capacitance is not high enough to support

the MOS channel, therefore the IGBT is turned off and able to block the forward voltage. The principles of forward voltage blocking for IGBT is the same as that for power diode. The depletion layer of the reverse biased N-P+ junction expands according to VCE. If the

drift region is long enough to accommodate the depletion layer, the N+ buffer layer shown in Fig. 2.10 is no longer necessary. This type of IGBT is called NPT IGBT and able to block reverse voltage by the PN- junction. If the reverse blocking capability is not required, it is possible to reduce the thickness of the drift region by the PT structure as shown in the figure.

There are several parasitic components in the structure of IGBT, as shown in Fig. 2.11. These components greatly affect the behavior of IGBT. The gate-emitter capacitance (CGE)

which also refers to as the input capacitance, is the capacitance between gate and channel. This capacitance consists ofCOX and the capacitance of depletion layer forms at the Si-oxide

interface, hence it varies withVGE. The gate-collector capacitance (CGC) which also refers to

as the Miller capacitance, is the combination ofCOX and the capacitance of depletion layer in

the drift region under the gate. This capacitance varies as the depletion layer area changes. during on-state, the depletion layer under gate disappears, hence the Miller capacitance

N+ P+ N+ N- drift region N+ buffer layer P Collector Emitter Gate SiO2 SiO2 CGE Cdep Rd CGC RSP CGE CGC RSP Rd Cdep Parasitic NPN transistor Parasitic PNP transistor Collector Emitter Gate Prastic MOS (a) (b)

Figure 2.11: (a) IGBT structure with parasitic components and (b) accurate IGBT equivalent circuit.

approximately equal to COX. During off-state, CGC is reduced since the depletion layer

capacitance now connected in series withCOX. Due to this feature, Miller capacitance could

affect the switching characteristics of IGBT and lead to the gate voltage plateau which will be detailed in the next section. The collector-emitter capacitance CCE is also referred to as

the output capacitance. CCE consists of both the depletion capacitance under the P-well

layer Cdep and the capacitance of the charge stored in the drift region. Its value affects the

rate of forward voltage change during switching dVCE/dt.

Furthermore, parasitic PNP and NPN transistors can be found in the IGBT structure, as shown in Fig. 2.11. Together, they can form a parasitic thyristor. Under some specific conditions, this thyristor could be activated, which is called latchup and can cause the IGBT to become uncontrollable. During on-state, holes are injected from the P collector to the N- drift region and finally enters P-well where they recombine with the electrons from the emitter metallisation. There are two path ways of this hole flow, lateral and vertical across the P-well. Due to the negative charge of the inversion layer, most of the holes are attracted to flow laterally under it. A lateral voltage drop is then developed by this hole flow and the

resistance of the P-well (RSP). Latchup occurs when this voltage is high enough to forward

bias the P+N+ junction. Latchup could also occur during turn-off whendV /dt is too large. During turn-off, the excess carriers stored in the drift region is removed and depletion layer builds up. IfdV /dtis too large, the discharging current will become large enough to forward bias the P+N+ junction and lead to the latchup of IGBT.

Obviously, latchup is not desired for IGBT operation, several modifications can be made to avoid it. In the device aspect, latchup can be avoid by reducing RSP. This can be

done by either reducing the lateral width of the N+ emitter region or increasing the doping concentration of the P-well. However, the doping concentration of the MOS channel region need to be kept relatively low to ensure the inversion layer could take place easily. In the circuit aspect, latchup can be avoid by slowing down the turn-off process to limit dV /dt. This could be accomplished by using a larger value of gate resistance (Rg), which limits the

gate discharging current.