Basic Physics of Solder Fatigue

Solder is widely used in the power semiconductor industry to form the electrical and me- chanical connection between the chip and substrate. Therefore, the ideal solder should have excellent electrical properties and mechanical strength. Also, the melting point of solder should not too high to damage the chip during soldering process. The most frequently used solders in power modules are based on tin-silver, indium, or tin-lead alloys [4]; these are soft materials with low melting temperature and high electrical conductivity. The chip consumes energy and generates heat when it is switching and conducting current. A potentially large amount of heat needs to conduct from the chip to the heatsink, through the solder and DCB, therefore a high thermal conductivity is desirable.

During the operation of power module, temperature cycles are generated due to the change of load conditions. Cyclic thermomechanical stress is induced at the solder layer due to the temperature cycle and CTE mismatch between the Si chip and DCB substrate. This cyclic stress will cause solder fatigue and possibly failure. Fatigue is defined as the process of progressive failure caused by repeated stress cycles which are well below the yield strength of the material [3]. The propagation of a fatigue crack is similar to the crack propagation process and is shown in Fig. 3.7. The thermomechanical shear stress produces a plastic zone

σ

a a

Δapl

Δael+Δapl

Figure 3.7: Illustration of fatigue crack propagation.

at the fatigue crack tip and causes the crack elongate by ∆a and create a new surface. ∆a

consists of the elastic deformation (∆ael) and plastic deformation (∆apl). ∆ael is released

after the stress is removed. However, the new surface extends the original crack by ∆apl due

to the permanent plastic deformation. Fig. 3.8 shows the hysteresis loop of this process for one stress cycle.

There are many models available to describe the solder fatigue damage [64]. They can be organised into three categories: strain based models [65], energy based models [66,67], and damage based models [68]. Energy based models estimate the lifetime by calculating the overall stress-strain hysteresis energy of the solder joint. The damage based models do the same job by calculating the accumulated damage caused by crack propagation. These two types of model require a FEA tool to obtain the stress-strain hysteresis loop hence are time consuming. The strain based models predict failure from calculated or experimentally determined shear strain. The Coffin-Manson model is one of the best known strain based models, as shown in Eqn. 3.3. Thermally induced strain at the solder layer can be derived from a three layer structure [69], as shown in Fig. 3.9.

The maximum stress appears at the edge and can be calculated using Eqn. 3.7, with β

as defined by Eqn. 3.8. Here, G stands for the shear modulus and E stands for the Young’s modulus of the related layer. The die and substrate are much more rigid than the solder, henceβLdie≪1 andtanh(βLdie)≈βLdie. Therefore, the maximum shear strain at the edge

σ

ε

Elastic zone

Plastic zone

Figure 3.8: Hysteresis loop for the solder fatigue process for one stress cycle.

Die (Si)

Substrate (Cu)

τ

h

h

h

L

Solder

of the solder joint can be expressed in the form of Eqn. 3.9. The lifetime is then linked with temperature cycles by substituting Eqn. 3.9 into the Coffin-Manson Law, as shown in Eqn.

3.10.

σmax =

Gsolder hsolder·β ·

(αsub−αdie)·∆Tj ·tanh(βLdie) (3.7) β2 = Gsolder hsolder · 1 Esubhsub + 1 Ediehdie (3.8) ǫmax = Ldie hsolder · (αsub−αdie)·∆Tj (3.9) Nf =a Ldie hsolder · (αsub−αdie)·∆Tj −b (3.10) This is the same as the bond wire failure, it needs to be examined whether the assumption of Coffin-Manson Law holds. According to Ochiai [70], the shear modulus of solder changes with temperature. It decreases from 10 Gpa at room temperature (25 ‰) to 5 GPa at 100 ‰. The minimum value is used to obtain the largest possible yield strain. The yield strength

of SnAg solder is around 30 MPa according to [71]. The yield strain of this solder can be calculated using Eqn. 3.6, giving a value of 6_×10−3_{. The typical thickness of the die-attach}

solder layer is from 50 to 100µm; the average value is used in this calculation. The length of the chip of the selected module is 4 mm and the CTE mismatch between Si and Cu is 14.5 ppm/K. Substituting these values into Eqn. 3.9 gives the minimum ∆Tj needed for plastic

deformation as 8 ‰. This is even lower than that required for the plastic deformation of Al

wire, thus the assumption of Coffin-Manson Law holds.

The solder fatigue process is complex. Some papers state that the lifetime is not only depends on the temperature cycle amplitude (∆Tj), but also the mean temperature (Tm),

modified the conventional Coffin-Manson relationship and proposed a model which considers

f, maximum junction temperature (Tjmax) and ∆Tj as variables [74], as shown in Eqn.

3.11. Here, Ea is the activation energy and k is the Boltzmann’s constant. However, more

experimental data is needed in order to extract the parameters of this model, which leads to a longer investigation and higher cost.

Nf =A·fB·∆Tja·exp Ea kTjmax (3.11)