The basics

The term VLSI, in its broadest sense, denotes the implementation of a digital or analog system, in very large scale integration, as well as all associated activities during the process of design and implementation of the system. Likewise, the term VLSI, in specific, means that the transistor count of the chip is larger than 10,000 (different sources quote different figures). The following table summarizes the transistor counts for various integration scales (the most frequently encoun-tered figures are given here):

SSI: more than 10 transistors per chip MSI: more than 100 transistors per chip LSI: more than 1,000 transistors per chip VLSI: more than 10,000 transistors per chip

As previously stated, the actual figures should not be taken unconditionally. Some sources quote the same figures, but refer to the gate count, as opposed to the transistor count. The number of transistors per gate ( N_{t g}) depends on the technology of the integrated circuit design, and on the fan-in (Nu). For instance:

NMOS (Si): N_{t g} = +1 N_u CMOS (Si): N_{t g} = 2N_u ECL (Si): N_{t g} = +3 N_u

In the case of GaAs technology used in the project described in this book, the following holds true:

E/D-MESFET (GaAs): N_{t g} = +1 N_u

Therefore, when we speak of the chip complexity, we have to stress the fact that our figures re-fer to one of the two counts (transistor count or gate count). The term “device” is often confus-ing, because some sources use it to denote the transistor, and others to denote the gate.

The VLSI design methodologies can be classified as: (a) design based on geometric symbols—

full-custom (FC) VLSI, (b) design based on logic symbols, and (c) design based on behavioral symbols—silicon compilation or silicon translation (ST). Design based on logic symbols can be divided further into three subclasses: (b1) standard cell (SC) VLSI, (b2) gate array (GA) VLSI, and (b₃) programmable logic (PL) VLSI. Or, to put it in another way:

VLSI

The figures in parentheses denote the number of VLSI mask layers necessary for the prefabri-cation process, or before the design of the chip is begun (the value before the comma), and the number of VLSI mask layers necessary for the final fabrication process, or after the chip design is complete (the value after the comma). The total number of VLSI mask layers is governed by the chosen fabrication technology and the chip realization technique.

The FC VLSI and the SC VLSI technologies require no prefabrication. The VLSI mask layers are created after the design process is completed. In the case of the FC VLSI, all necessary VLSI mask layers are created directly from the circuit design based on the geometric symbols. In the case of the SC VLSI, one extra step is required, namely the translation of the design based on the logic symbols into the design based on the geometric symbols. Among the most renowned US manufacturers of VLSI chips based on the SC and FC technologies are VLSI Technology. (Sili-con) and TriQuint (GaAs).

The GA VLSI technology requires all VLSI mask layers prefabricated, except one or two, which define the interconnects. Only those layers are specified by the designer, after the design process is complete. Among the most renowned US manufacturers of the GA VLSI chips are Ho-neywell (Silicon) and Vitesse (GaAs).

The PL VLSI technology has all mask layers prefabricated, and there is no final fabrication.

Only the interconnects have to be activated after the design is completed. The interconnects are prefabricated, along with the rest of the chip. This is achieved by writing the appropriate contents into the on-chip ROM or RAM memory. Among the most renowned US manufacturers of the PL VLSI chips are Actel, Altera, AT&T, Cypress, Lattice, and Xilinx.

The ST VLSI technology is based on FC VLSI, SC VLSI, GA VLSI, or PL VLSI, in the chip fabrication domain; it is based on general-purpose HLLs (like C) or special-purpose HLLs (like HDLs) in the chip design domain.

All these methods have the common basic design activities: (a) logic entry and schematic cap-ture, (b) logic and timing testing, and (c) placement and routing. These activities have a specific form in the case of FC VLSI and ST VLSI (these two methods will not be further elaborated here).

For the three design methodologies based on logic symbols, the schematic entry and log-ic/timing testing are identical. The most striking differences, however, occur in the placement and routing arena.

These differences are due to the differing levels of flexibility of placement of chip elements in different technologies, which is, in turn, governed by the number of prefabricated mask layers.

An explanation follows.

With SC VLSI no mask layers are prefabricated, leaving the designer with complete freedom in placement. With GA VLSI there are N – 1 or N – 2 mask layers prefabricated, so the placement freedom is significantly reduced. With PL VLSI all mask layers are prefabricated, leaving minim-al placement flexibility.

In practical terms, the basic elements of SC VLSI chips have equal heights and different widths, the latter dimension being a function of the standard cell complexity. Standard cells are aligned in channels to ease the burden of the placement and routing software. Interconnects are grouped in the interconnect channels. A typical layout is given in Figure 4.1. The height of a Figure 4.1. Sketch of the semiconductor wafer containing a large number of chips designed us-ing the SC (Standard Cell) VLSI methodology. Symbol L refers to logic channels, and symbol I refers to interconnect channels. The channels containing standard cells have the same width, and are not equidistant. The channels containing connections have a varying width—their widths are governed by the number and the structure of connections that have to be made. They take up a relatively small proportion of the chip area (around 33% in this sketch). The total chip area is as big as the implemented logic requires (the chip utilization is always close to 100%).

standard cell channel is equal for all channels, because the standard cell family, the chosen tech-nology, and design methodology define it. The height of an interconnect channel depends on the number of interconnects, and it differs from channel to channel on the same chip. In plain Eng-lish, this means that the standard cell channels are not equidistant.

In GA VLSI, the basic elements, the gates, have all the same dimensions (all gates share the same complexity). The gates are placed in the gate channels during the prefabrication process.

The interconnects are realized through prefabricated interconnect channels. The interconnects are made for two purposes: to form RTL elements, and to connect them in order to make the de-signed VLSI system. A typical layout is shown in Figure 4.2. In this case, not only the gate chan-Figure 4.2. Sketch of the chip designed using the GA (Gate Array) VLSI methodology. The channels that contain the gates are of the same width, and are equidistant. Symbol L refers to log-ic channels, and symbol I refers to interconnect channels. The channels that contain the connec-tions are also of the same width—their widths are predetermined during the prefabrication process. They take up more chip area (around 50% in the sketch). The total chip area is always bigger than the area required by the logic, because the prefabricated chips of standard dimensions are used (the chip utilization is virtually always below 100%—the designers are usually very happy if they reach 90%).

Figure 4.3. Sketch of the chip designed using the PL (Programmable Logic) VLSI methodology.

Symbol L refers to logic channels, and symbol I refers to interconnect channels. The areas con-taining the macrocells (shaded) take up only a fraction of the chip area (around 25% in the sketch). The channels containing the connections take up the rest of the area (around 75% in the sketch), and their intersections contain the interconnection networks that are controlled using ei-ther RAM (e.g., XILINX) or ROM (e.g., ALTERA) memory elements. The sketch shows one of the many possible internal architectures that are frequently implemented. The total chip area is always quite bigger than the area required by the logic, because the prefabricated chips of stan-dard dimensions are used (the chip utilization is virtually always below 100%—the designers are usually very happy if they reach 80%).

nels, but the interconnect channels as well, are fixed in size. In other words—gate channels are equidistant.

In PL VLSI, the basic elements, the macrocell blocks (logic elements of a significant complex-ity), are prefabricated and interconnected. A typical layout is given in Figure 4.3. The intersection of channels contains the interconnect networks, controlled by the contents of RAM or ROM memory.

The differences between these three design methodologies influence the design cost and the fabrication cost.

The design cost is made up from two components: (a) creative work that went into the design, and (b) design cost in specific.

The cost of the creative work depends on the scientific and technical complexity of the prob-lem that is being solved through the VLSI chip realization.

The design cost in specific depends on the number of engineer hours that went into the design process. No matter what technology was chosen (SC, GA, or PL VLSI), the cost of schematic entry and logic testing is about equal, because the complexity of that process depends on the dia-gram complexity, and not on the chip design methodology. However, the placement and routing cost is at its peak in SC VLSI, and at its bottom in PL VLSI. This is a consequence of the great flexibility offered by the SC VLSI, which takes a lot of engineer hours to be fully utilized. This, in turn, rises the cost of the placement and routing process. On the other side, the hours spent in the placement and routing increase the probability that the chip will have a smaller VLSI area, thus reducing the production run cost.

Chip fabrication cost is made up from two basic components: (a) cost of making masks, and (b) production run cost, after mask layers have been made.

In SC VLSI, the complete cost of making N mask layers falls to the individual buyers, because no masks are made before the design, and different buyers can not share the cost of any kind.

However, when the production starts, the unit cost of SC VLSI chips is lower, because they prob-ably have the smallest VLSI area for the same system complexity. This is the consequence of the extremely flexible placement and routing process, thus maximizing the number of logic elements per area unit. The interconnect channels can be narrow (only the area absolutely needed by the interconnects will be occupied). In general, chip cost is proportional to the chip VLSI area raised to the power of x, where x is typically between 2 and 3.

In GA VLSI, the cost of making the first N – 1 or N – 2 mask layers is shared between all buy-ers, because they are the same for everybody. Since (a) cost is shared, (b) large scale production reduces cost per unit, and (c) only one or two mask layers are specific, the total cost of making masks is smaller. On the other hand, the production cost of GA VLSI chips is higher, because the system of a given complexity requires larger VLSI area than in the case of SC VLSI. This is due to the significantly restricted placement and routing flexibility, which leads to less efficient logic element packing. The interconnect channels are equidistant, and are frequently wider than neces-sary for the specific design. Also, the chip has standard dimensions, and part of it always remains unused, if the first smaller standard chip would not accommodate the design.

In PL VLSI, the cost of all N mask layers is shared between the buyers, since all mask layers are the same for everybody. Thus, the mask making cost is minimal. However, the production cost of these chips is the highest, because they offer the smallest logic element packing density, due to their internal structure. This is due to the minimal flexibility in the placement and routing, and to the large VLSI area devoted solely to the interconnection purposes. Also, since the chips are standard, parts remain unused every time.

When all these cost determining factors are considered, the following can be said. If large scale production will follow, it is best to use the FC VLSI design methodology. In the case of smaller, but still relatively large series, it is best to use the SC VLSI design methodology. In the case of not particularly large series, the best solution to the problem is the GA VLSI design me-thodology. For small series and individual chips, it is best to design for the PL VLSI, or the ST VLSI. The boundaries are somewhat blurred, since they depend on the non-technical parameters, but one can frequently stumble upon some numbers (to be understood only as guidelines; N_sp refers to the number of chips in the serial production):

FC:

The typical dependencies of total cost (C) on the number of chips in the series (Nsp) are given in Figure 4.4. It is obvious from the figure that the initial cost (at Nsp = 0) is the largest for FC VLSI, then drops off through SC and GA VLSI, to reach its minimum for PL VLSI and ST VLSI.

CROSS SECTION OF PHYSICAL STRUCTURE

Figure 4.4. The dependency of the cost with respect to the number of chips manufactured. The C-axis represents the total cost of the design and manufacturing processes, for the series compris-ing of N_sp VLSI chips. The value C₀ that corresponds to N_sp = 0 represents the sum of the two components. They are: (a) the cost of the design, and (b) the cost of all the masks that have to be made after the design is complete.

PTUB MASK

n-SUBSTRATE

p-WELL FIELD OXIDE (FOX) 4-6 µm DEEP

PTUB

Figure 4.5.a. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #1.

CROSS SECTION OF PHYSICAL STRUCTURE

(SIDE VIEW) MASK (TOP VIEW)

THINOXIDE MASK

n-SUBSTRATE

p-WELL THINOXIDE (~ 50 nm)

THINOXIDE Figure 4.5.b. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #2.

CROSS SECTION OF PHYSICAL STRUCTURE

(SIDE VIEW) MASK (TOP VIEW)

POLYSILICON MASK

n-SUBSTRATE

p-WELL POLYSILICON

POLYSILICON Figure 4.5.c. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #3.

CROSS SECTION OF PHYSICAL STRUCTURE

(SIDE VIEW) MASK (TOP VIEW) p-PLUS MASK (POSITIVE)

n-SUBSTRATE

p-WELL p-TRANSISTOR

p+ p+

p-PLUS + Figure 4.5.d. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #4.

CROSS SECTION OF PHYSICAL STRUCTURE

(SIDE VIEW) MASK (TOP VIEW)

p-PLUS MASK (NEGATIVE)

n-SUBSTRATE p-WELL n-TRANSISTOR

p+ p+ n+ n+

pPLUS -Figure 4.5.e. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #5.

CROSS SECTION OF PHYSICAL STRUCTURE

(SIDE VIEW) MASK (TOP VIEW)

CONTACT MASK

n-SUBSTRATE p-WELL CONTACT CUTS

p+ p+ n+ n+

CONTACT Figure 4.5.f. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #6.

CROSS SECTION OF PHYSICAL STRUCTURE

(SIDE VIEW) MASK (TOP VIEW)

METAL MASK

n-SUBSTRATE p-WELL METAL

p+ p+ n+ n+

METAL

Figure 4.5.g. The processes of implementation of a silicon CMOS transistor, and the geometric structure of the corresponding VLSI masks: mask #7.