The knowledge obtained through some kind of formal education can be treated in only one way—as the foundation for further development. Since the field treated here is practical in its nature, lots of hard practical work is necessary. However, the field expands at a fast pace, and lots of new reading is absolutely necessary. The references listed below represent the ground that has to be mastered, before one decides to go into the opening of new horizons.
10.1. References
This section contains all references used directly in the text of this book. A part of these refer-ences contains the facts used to write the book. Other referrefer-ences contain the examples created with the knowledge covered by the book.
[Altera92] “Altera User Configurable Logic Data Book,” Altera, San Jose, California, USA, 1992.
[ArcBae86] Archibald, J., Baer, J. L., “Cache Coherence Protocols: Evaluation Using a Multi-processor Simulation Model,” ACM Transactions on Computer Systems, Novem-ber 1986, pp. 273–298.
[Armstr89] Armstrong, J. R., “Chip Level Modeling With VHDL,” Prentice-Hall, Englewood Cliffs, New Jersey, USA, 1989.
[BožFur93] Božaniæ, D., Fura, D., Milutinoviæ, V., “Simulation of a Simple RISC Processor,”
Application Note D#001/VM, TD Technologies, Cleveland Heights, Ohio, USA, January 1993.
[Brown92] Brown, R., et al., “GaAs RISC Processors,” Proceedings of the GaAs IC Sympo-sium, Miami, Florida, USA, 1992.
[Bush92] Bush, W. R., “The High-Level Synthesis of Microprocessors Using Instruction Frequency Statistics,” ERL Memorandum M92/109, University of California at Berkeley, Berkeley, California, USA, May 1992.
[CADDAS85] “CADDAS User’s Guide,” RCA, Camden, New Jersey, 1985.
[Distante91] Distante, F., Sami, M. G., Stefanelli, R., Storty-Gajani, G., “A Proposal for Neural Macrocell Array,” in Sami, M., et al., “Silicon Architectures for Neural Nets,” El-sevier Science Publishers, 1991.
[Endot92a] “ENDOT ISP’ User’s Documentation,” TDT, Cleveland Heights, Ohio, USA, 1992.
[Endot92b] “ENDOT ISP’ Tutorial/Application Notes,” TDT, Cleveland Heights, Ohio, USA, 1992.
[Ferrar78] Ferrari, D., “Computer Systems Performance Evaluation,” Prentice- Hall, Engle-wood Cliffs, New Jersey, USA, 1978.
[FeuMcI88] Feugate, R. J., McIntyre, S. M., “Introduction to VLSI Testing,” Prentice-Hall, Englewood Cliffs, New Jersey, USA, 1988.
[Flynn95] Flynn, M. J., “Computer Architecture: Pipelined and Parallel Processors,” Stan-ford University Press, Palo Alto, California, USA, 1995.
[ForMil86] Fortes, J. A. B., Milutinoviæ, V., Dick, R., Helbig, W., Moyers, W., “A High-Level Systolic Architecture for GaAs,” Proceedings of the ACM/IEEE 19th Hawaii In-ternational Conference on System Sciences, Honolulu, Hawaii, USA, January 1986, pp. 238–245.
[Gay86] Gay, F., “Functional Simulation Fuels Systems Design,” VLSI Design Technology, April 1986.
[GilGro83] Gill, J., Gross, T., Hennessy, J., Jouppi, N., Przybylski, S., Rowen, C., “Summary of MIPS Instructions,” TR#83-237, Computer System Laboratory, Stanford Uni-versity, Palo Alto, California, USA, 1983.
[GroHen82] Gross, T. R., Hennessy, J. L., “Optimizing Delayed Branches,” Proceedings of the 15th Annual Workshop on Microprogramming, MICRO-15, 1982, pp. 114–120.
[HanRob88] Handgen, E., Robbins, B., Milutinoviæ, V., “Emulating a CISC with GaAs Bit-Slice Components,” IEEE TUTORIAL ON MICROPROGRAMMING, Los Alamitos, California, USA, January 1988, pp. 70–101.
[HelMil89] Helbig, W., Milutinoviæ, V., “A DCFL E/D-MESFET GaAs 32-bit Experimental RISC Machine,” IEEE Transactions on Computers, February 1989, pp. 263–274.
[HenPat90] Hennessy, J. L., Patterson, D. A., “Computer Architecture: A Quantitative Ap-proach,” Morgan Kaufmann Publishers, San Mateo, California, USA, 1990.
[HoeMil92] Hoevel, L., Milutinoviæ, V., “Terminology Risks with the RISC Concept in the Risky RISC Arena,” IEEE Computer, Vol. 24, No. 12, January 1992, p. 136.
[LipSch90] Lipsett, R., Schaefer, C., Ussery, C., “VHDL: Hardware Description and Design,”
Kluwer Academic Publishers, Boston, Massachusetts, USA, 1990.
[LOGSIM85] “LOGSIM User’s Guide,” RCA, Camden, New Jersey, USA, 1985.
[McClus88] McCluskey, E. J., “Built-In Self-Test Structures,” IEEE Design and Test of Com-puters, April 1985, pp. 29–35.
[McNMil87] McNeley, K., Milutinoviæ, V., “Emulating a CISC with a RISC,” IEEE Micro, February 1987, pp. 60–72.
[MilBet89a] Milutinoviæ, V., Bettinger, M., Helbig, W., “On the Impact of GaAs Technology on Adder Characteristics,” IEE Proceedings Part E, May 1989, pp. 217–223.
[MilFur86] Milutinoviæ, V., Fura, D., Helbig, W., “An Introduction to GaAs Microprocessor Architecture for VLSI, IEEE Computer, March 1986, pp. 30–42.
[MilFur87] Milutinoviæ, V., Fura, D., Helbig, W., Linn, J., “Architecture/Compiler Synergism in GaAs Computer Systems,” IEEE Computer, May 1987, pp. 72–93.
[MilLop87] Milutinoviæ, V., Lopez-Benitez, N., Hwang, K., “A GaAs-Based Architecture for Real-Time Applications,” IEEE Transactions on Computers, June 1987, pp. 714–
727.
[MilPet94] Miliæev, D., Petkoviæ, Z., Milutinoviæ, V., “Using N.2 for Simulation of Cache Memory: Concave Versus Convex Programming in ISP’,” Application Note D#003/VM, TD Technologies, Cleveland Heights, Ohio, USA, January 1994.
[MilPet95] Milutinoviæ, V., Petkoviæ, Z., “Ten lessons learned from a RISC design,” IEEE Computer, March 1995, pp. 120.
[Miluti88a] Milutinoviæ, V., “Microprocessor Architecture and Design for GaAs Technology,”
Microelectronics Journal, Vol. 19, No. 4, July/August 1988, pp. 51–56.
[Miluti90] Milutinoviæ, V., Editor, “Microprocessor Design for GaAs Technology,” Pren-tice-Hall, Englewood Cliffs, New Jersey, USA, 1990.
[Miluti92a] Milutinoviæ, V., “RISC Architectures for Multimedia and Neural Networks Ap-plications,” Tutorial of the ISCA-92, Brisbane, Queensland, Australia, May 1992.
[Miluti92b] Milutinoviæ, V., Editor, “Introduction to Microprogramming,” Prentice Hall, En-glewood Cliffs, New Jersey, USA, 1992 (Forward: M. Wilkes).
[Miluti93] Milutinoviæ, V., “RISC Architectures for Multimedia and Neural Networks Ap-plications,” Tutorial of the HICSS-93, Koloa, Hawaii, USA, January 1993.
[Miluti96] Milutinoviæ, V., “Catalytic Migration: A Strategy for Creation of Technology-Sensitive Microprocessor Architectures,” Acta Universitatis, Niš, Serbia, Yugosla-via, 1996.
[MOSIS93] “MOSIS Fabrication Facility User’s Guide,” MOSIS, Xerox, Palo Alto, Califor-nia, USA, 1993.
[MP2D85] “MP2D User’s Guide,” RCA, Camden, New Jersey, USA, 1985.
[Mudge91] Mudge, T. N., et al., “The Design of a Micro-Supercomputer,” IEEE Computer, January 1991, pp. 57–64.
[Myers82] Myers, G. J., “Advances in Computer Architecture,” John Wiley and Sons, New York, New York, USA, 1982.
[PatDit80] Patterson, D. A., Ditzel, D. R., “Case for the Reduced Instruction Set Computer,”
Computer Architecture News, Vol. 8, No. 6, October 15, 1980, pp. 25–33.
[PatHen94] Patterson, D., Hennessy, J., “Computer Organization and Design,” Morgan Kauf-mann Publishers, San Mateo, California, USA, 1994.
[PetMil94] Petkoviæ, Z., Milutinoviæ, V., “An N.2 Simulator of the Intel i860,” Application Note D#004/VM, TD Technologies, Cleveland Heights, Ohio, USA, January 1994.
[RosOrd84] Rose, C. W., Ordy, G. M., Drongowski, P. J., “N.mpc: A Study in Universi-ty-Industry Technology Transfer,” IEEE Design and Test of Computers, February 1984, pp. 44–56.
[Tabak90] Tabak, D., “Multiprocessors,” Prentice-Hall, Englewood Cliffs, New Jersey, USA, 1990.
[Tabak95] Tabak, D., “Advanced Microprocessors,” McGraw-Hill, New York, New York, USA, 1995.
[Tanner92] “Tanner Tools User’s Documentation,” Tanner Research, Pasadena, California, USA, 1992.
[TomMil93a] Tomaševiæ, M., Milutinoviæ, V., “Tutorial on Cache Consistency Schemes in Multiprocessor Systems: Hardware Solutions,” IEEE Computer Society Press, Los Alamitos, California, USA, 1993.
[TomMil93b] Tomaševiæ, M., Milutinoviæ, V., “Using N.2 in a Simulation Study of Snoopy Cache Coherence Protocols for Shared Memory Multiprocessor Systems,” Appli-cation Note D#002/VM, TD Technologies, Cleveland Heights, Ohio, USA, Janu-ary 1993.
[TomMil94a] Tomaševiæ, M., Milutinoviæ, V., “Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors: Part 1,” IEEE Micro, October 1994, pp. 52–64.
[TomMil94b] Tomaševiæ, M., Milutinoviæ, V., “Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors: Part 2,” IEEE Micro, December 1994, pp. 61–
66.
[Trelea88] Treleaven, P., et al., “VLSI Architectures for Neural Networks,” IEEE Micro, De-cember 1988.
[VHDL87] “IEEE Standard VHDL Language Reference Manual,” IEEE, Los Alamitos, Cali-fornia, USA, 1987.
[VlaMil88] Vlahos, H., Milutinoviæ, V., “A Survey of GaAs Microprocessors,” IEEE Micro, February 1988, pp. 28–56.
[WesEsh85] Weste, N., Eshraghian, K., “Principles of CMOS VLSI Design,” Addison Wesley, Reading, Massachusetts USA, 1985.
[Wulf81] Wulf, W. A., “Compilers and Computer Architecture,” IEEE Computer, July 1981.
[Xilinx92] “XC3000 Logic Cell Array Family Technical Data,” Xilinx, Palo Alto, California, USA, 1992.
161
10.2. Suggestions
Suggestions for further reading include two types of texts. The first group of texts includes the material to help about the depth of knowledge (e.g., the references listed here and their follow ups). The second group of texts includes the material to help about the breath of knowledge (e.g., from specialized journals and from proceedings books of the major conferences in the field).
[AntMil92] Antognetti, P., Milutinoviæ, V., Editors, “Neural Networks: Concepts, Applica-tions, and ImplementaApplica-tions,” Prentice-Hall, Englewood Cliffs, New Jersey, USA, 1992. Four-volume series (Forward: L. Cooper, Nobel laureate, 1972).
[FurMil87] Furht, B., Milutinoviæ, V., “A Survey of Microprocessor Architectures for Memo-ry Management,” IEEE Computer, March 1987, pp. 48–67.
[GajMil87] Gajski, D., Milutinoviæ, V., Siegel, H. J., Furht, B., (Editors), “Computer Archi-tecture,” IEEE Computer Society Press, Los Alamitos, California, USA, 1987.
[GimMil87] Gimarc, C., Milutinoviæ, V., “A Survey of RISC Architectures of the Mid 80’s,”
IEEE Computer, September 1987, pp. 59–69.
[HenJou83] Hennessy, J., Jouppi, N., Przybylski, S., Rowen, C., Gross, T., “Design of a High Performance VLSI Processor,” TR#83/236, Computer Systems Laboratory, Stan-ford University, Palo Alto, California, USA, 1983.
[Hollis87] Hollis, E. E., “Design of VLSI Gate Array ICs,” Prentice Hall, Englewood Cliffs, New Jersey, USA, 1987.
[Kateve83] Katevenis, M. G. H., RISC Architectures for VLSI, TR#83/141, University of Cal-ifornia at Berkeley, Berkeley, CalCal-ifornia, USA, October 1983.
[KonWoo87] Kong, S., Wood, D., Gibson, G., Katz, R., Patterson, D., “Design Methodology of a VLSI Multiprocessor Workstation,” VLSI Systems, February 1987.
[LeuSha89] Leung, S. S., Shaublatt, M. A., “ASIC System Design with VHDL: A Paradigm,”
Kluwer Academic Publishers, Boston, Massachusetts, USA, 1989.
[MilBet89b] Milutinoviæ, V., Bettinger, M., Helbig. W., “Multiplier/Shifter Design Trade-offs in GaAs Microprocessors,” IEEE Transactions on Computers, June 1989, pp. 874–880.
[MilCrn88] Milutinoviæ, V., Crnkoviæ, J., Houstis, K., “A Simulation Study of Two Distri-buted Task Allocation Procedures,” IEEE Transactions on Software Engineering, January 1988, pp. 54–61.
[MilFor86] Milutinoviæ, V., Fortes, J., Jamieson, L., “A Multicomputer Architecture for Real-Time Computation of a Class of DFT Algorithms,” IEEE Transactions on ASSP, October 1986, pp. 1301–1309.
[MilFur88] Milutinoviæ, V., Fura, D., Editors, “GaAs Computer Design,” IEEE Computer Society Press, Los Alamitos, California, USA, 1988.
[MilFur91] Milutinoviæ, V., Fura, D., Helbig, W., “Pipeline Design Tradeoffs in a 32-bit GaAs Microprocessor,” IEEE Transactions on Computers, November 1991, pp. 1214–1224.
[MilMil87] Milutinoviæ, D., Milutinoviæ, V., Souèek, B., “The Honeycomb Architecture,”
IEEE Computer, April 1987, pp. 81–83.
[MilSil86] Milutinoviæ, V., Silbey, A., Fura, D., Keirn, K., Bettinger, M., Helbig, W., Heag-garty, W., Ziegert, R., Schellack, R., Curtice, W., “Issues of Importance for GaAs Microcomputer Systems,” IEEE Computer, October 1986, pp. 45–57.
[Miluti80a] Milutinoviæ, V., “Suboptimum Detection Procedure Based on the Weighting of Partial Decisions, IEE Electronics Letters, 13th March 1980, pp. 237–238.
[Miluti80b] Milutinoviæ, V., “Comparison of Three Suboptimum Detection Procedures,” IEE Electronics Letters, 14th August 1980, pp. 683–685.
[Miluti85a] Milutinoviæ, V., “Generalized WPD Procedure for Microprocessor- Based Signal Detection,” IEE Proceedings Part F, February 1985, pp. 27–35.
[Miluti85b] Milutinoviæ, V., “A Microprocessor-oriented Algorithm for Adaptive Equaliza-tion,” IEEE Transactions on Communications, June 1985, pp. 522–526.
[Miluti86a] Milutinoviæ, V., “GaAs Microprocessor Technology,” IEEE Computer, October 1986, pp. 10–15.
[Miluti86b] Milutinoviæ, V., Editor, “Advanced Microprocessors and High-Level Language Computer Architecture,” IEEE Computer Society Press, Los Alamitos, California, USA, 1986.
[Miluti87] Milutinoviæ, V., “A Simulation Study of the Vertical Migration Microprocessor Architecture,” IEEE Transactions on Software Engineering, December 1987, pp. 1265–1277.
[Miluti88b] Milutinoviæ, V., “A Comparison of Suboptimal Detection Algorithms for VLSI,”
IEEE Transactions on Communications, May 1988, pp. 538–543.
[Miluti88c] Milutinoviæ, V., Editor, “Computer Architecture,” North-Holland, New York, New York, USA, 1988 (Forward: K. Wilson, Nobel laureate, 1982).
[Miluti89a] Milutinoviæ, V., Editor, “Microprogramming and Firmware Engineering,” IEEE Computer Society Press, Los Alamitos, California, USA, 1989.
[Miluti89b] Milutinoviæ, V., Editor, “High-Level Language Computer Architecture”, Freeman Computer Science Press, Rockville, Maryland, USA, 1989 (Forward: M. Flynn).
[Miluti89c] Milutinoviæ, V., “Mapping of Neural Networks onto the Honeycomb Architec-ture,” Proceedings of the IEEE, Vol. 77, No. 12, December 1989, pp. 1875–1878.
[PatSeq82] Patterson, D. A., Sequin, C. H., “A VLSI RISC,” IEEE COMPUTER, September 1982, pp. 8–21.
[PerLak91] Perunièiæ, B., Lakhani, S., Milutinoviæ, V., “Stochastic Modeling and Analysis of Propagation Delays in GaAs Adders”, IEEE Transactions on Computers, January 1991, pp. 31–45.
[PrzGro84] Przybylski, S., Gross, T. R., Hennessy, J. L. Jouppi, N. P., Rowen, C., “Organiza-tion and VLSI Implementa“Organiza-tion of MIPS,” TR#84-259, Computer Systems Labora-tory, Stanford University, Palo Alto, California, USA, 1984.
[Sherbu84] Sherburne, R. W. Jr., Processor Design Tradeoffs in VLSI,” TR#84/173, Universi-ty of California at Berkeley, Berkeley, California, USA, April 1984.
[SilMil86] Silbey, A., Milutinoviæ, V., Mendoza Grado, V., “A Survey of High- Level Lan-guage Architectures, IEEE Computer, August 1986, pp. 72–85.
[TarMil94] Tartalja, I., Milutinoviæ, V., “Tutorial on Cache Consistency Schemes in Multi-processor Systems: Software Solutions,” IEEE Computer Society Press, Los Ala-mitos, California, USA, 1994.
[Ullman84] Ullman, J. D., “Computational Aspects of VLSI,” Freeman Computer Science Press, Rockville, Maryland, USA, 1984.