Limitations of the Linear Buffer Model.
7.2.3. Behavioral Modeling of the Basic CMOS Buffer
The models shown here are similar to the linear—behavioral models in Section 7.2.2. The difference is that these models have I-V curves that mimic the transistor curves instead of approximating it with a straight line. Since these models are defined by a transistor curve and a curve for the time behavior, and are not defined by detailed transistor data such as used in a traditional SPICE model, these models are particularly useful when communicating between different companies. This is because a model can be created that does not contain detailed information about silicon processes and other proprietary information.
A behavioral model consists of an I-V curve and a time curve just as in the linear— behavioral models already discussed. This transistor curve should generally be based on known device characteristics. These characteristics may be supplied by the designer or provided by the vendor. Often, early simulations will be performed using one of the linear models in Section 7.2.2 to determine necessary requirements. The results of the linear simulations may be given to circuit designers or vendors as the initial design targets to create real buffers. Then simulated data based on actual transistor designs (or measured data on the devices) can be used to create a behavioral model.
The structure of a behavioral model is shown in Figure 7.20. For each transistor in the model, an I-V curve and a V-T curve is given for both the turn-on and turn-off cycles. The V-T
curves are the shape of the actual voltage waveforms driven into an assumed load. The assumed load used in constructing the model does not have to correspond to the physical
load that is expected in a system. The simulator takes as input the load used to construct the model and adjusts the model to different load conditions. However, there may be increased accuracy if the load used to construct the model is similar to the load present in the system. Typically, a load of 50 Ω is chosen; however, other loads can be used to construct the model. Since a pull-up device, for instance, has no capacity to pull down the output, the turn-off V-T curve is constructed from assuming a pull-down load even if no such load exists in the system. Figure 7.21 shows some assumed loads used to construct both the V-T curves for both the pull-up and pull-down devices in a CMOS buffer.
Figure 7.20: Requirements of each device (PMOS and NMOS) in a behavioral model: (a)
Figure 7.21: Creating the V-T curves in a behavioral model.
Generally, the simulator will construct intermediate I-V curves other then the input I-V curve to be used during voltage transitions. The intermediate curves will be chosen such that the time behavior during the transition will mimic the V-T curve input to the model. This behavior is illustrated in Figure 7.22. Note in the V-T curve shown in Figure 7.22 that there is no data point near the threshold (generally, Vdd/2) at which timing is measured. This may induce a
timing inaccuracy, depending on how the simulator (or the model maker) extrapolated points on the V-T curve near the threshold. Generally, models should be defined with at least one point at or near the timing threshold.
The I-V and V-T curves used to construct the model can be created from actual silicon measurements or from simulations with full transistor models. In either case, the question arises as to what effects to include in the model. For instance, if a V-T curve is determined directly from measurement of a device that has capacitance present at the output node, the capacitance will obviously affect the shape of the V-T curve measured. This will result in the capacitance being virtually included in the model through its effect on the V-T behavior. If the capacitance under question will actually be present in a physical system, such as on-die capacitance and package capacitance, this has no effect on the driving characteristics of the buffer. However, if the capacitance is embedded in the V-T curve in such a manner, the capacitance will not be modeled properly when the driver node is receiving a voltage
waveform such as a reflection. For this reason it is preferable to create the V-T curve with as little capacitance as possible at the output node and then add the capacitance back into the final model as a lumped element. Some capacitance cannot easily be subtracted from the model, particularly if the models are created from direct measurement.
As a final note, it should be mentioned that the behavioral model should be constructed with an I-V curve extending in voltage far beyond the expected operation of the device. This accounts for system effects such as a large overshoot. Typically, if the model is anticipated to be used from 0 to Vdd, the I-V curve of the model should be extended from -Vdd to 2Vdd to