Digital Timing Analysis

OVERVIEW

We have now covered everything that is needed to model a signal propagating from one component to another. We have covered the details of predicting signal integrity variations and estimating timing impacts caused by a plethora of nonideal high-speed phenomenon. However, this is not sufficient to properly design a digital system. The next step is to coordinate the system so that the individual components can talk to each other. This involves timing the clocks or component strobes so that they can latch in the data at the correct time so that the setup- and hold-time requirements of the receiving components are not violated.

In this chapter we describe the basic timing equations for common-clock and source synchronous bus architectures. The timing equations will allow the engineer to track each timing component that affects system performance, set design targets, calculate maximum bus speeds, and compute timing margins.

8.1. COMMON-CLOCK TIMING

In a common-clock timing scheme, a single clock is shared by driving and receiving agents on a bus. Figure 8.1 depicts a common-clock front-side bus similar to some personal computer designs (a front-side bus is the interface between the processor and the chipset). This example depicts the case when the processor is sending a bit of data to the chipset. The internal latches, which are located at each I/O cell, are shown. A complete data transfer requires two clock pulses, one to latch the data into the driving flip-flop and one to latch the data into the receiving flip-flop. A data transfer occurs in the following sequence:

Figure 8.1: Block diagram of a common-clock bus.

1. The processor core provides the necessary data at the input of the processor flip-flop (Dp).

2. System clock edge 1 (clk in) is transmitted through the clock buffer and propagates down a transmission line and latches that data from Dp to the output Qp at the

processor.

3. The signal on Qp propagates down the line to Dc and is latched in by clock edge 2. The

data is then available to the core of the chipset.

Based on the foregoing sequence, a few fundamental conclusions can be made. First, the delay of the circuitry and the transmission lines must be smaller than the cycle time. This is because each time a signal is transmitted from one component to another, it requires two clock edges: the first to latch the data at the processor to the output buffer (Qp), and the

second to latch the data at the input of the chipset receiver flip-flop into the core. This places an absolute theoretical limit on the maximum frequency that a common-clock bus can operate. The limitation stems from the total delay of the circuitry and the PCB traces, which

must remain less than the delay of one clock cycle. To design a common-clock bus, each of these delays must be accounted for and the setup and hold requirements of the receiver, which are the minimum times that data must be held before and after a clock to ensure correct latching, must be satisfied.

8.1.1. Common-Clock Timing Equations

To derive the timing equations for a common-clock bus, refer to the timing diagram in Figure 8.2. Each of the arrows represents a delay in the system and is labeled in Figure 8.1. The solid lines represent the timing loop used to derive the equation for the setup margin, and the dashed lines represent the loop used for the hold margin. How to use the timing loop to construct timing equations will become evident shortly.

Figure 8.2: Timing diagram of a common-clock bus.

The delays are separated into three groups: Tco's, flight times, and clock jitter. The Tco (time

from clock to output) is simply the time it takes for a data bit to appear at the output of a latch or a buffer once it has been clocked in. The flight times, Tflt, are simply the delays of the

transmission lines on the PCB. Clock jitter, Tjitter, generally refers to the cycle-to-cycle

variations of the clock period. Period jitter, for instance, will cause the period of the clock to vary from cycle to cycle, which will affect the timing of the clock edge. For the purposes here, jitter will be considered as a variation that may cause the clock to exhibit a temporary

change in clock period.

Setup Timings.

To latch a signal into a component, it is necessary that the data signal arrive prior to the clock. The receiver setup time dictates how long the data must be valid before it can be

clocked in. In a common-clock scenario, the data are latched to the output of the driver with one clock edge and latched into the receiver with the next clock edge. This means that the sum of the circuit and transmission line delays in the data path must be small enough so that the data signal will arrive at the receiver (Dc) sufficiently prior to the clock signal (clkC). To

ensure this, we must determine the delays of the clock and the data signals arriving at the receiver and ensure that the receiver's setup time has been satisfied. Any extra time in excess of the required setup time is the setup margin.

Refer to the solid arrows in the timing diagram of Figure 8.2. The timing diagram depicts the relationship between the data signal and the clocks both at the driver and receiver. The arrows represent the various circuit and transmission line delays in the data and clock paths. The solid arrows form a loop, which is known as the setup timing loop. The left-hand portion of the loop represents the total delay from the first clock edge to data arriving at the input of the receiver (Dc). The right-hand side of the loop represents the total delay of the receiver

clock.

To derive the setup equation, each side of the setup loop must be examined. First, let's examine the total delay from the first clock edge to data arriving at the input of the receiver. The delay is shown as (see Figure 8.1)

(8.1)

where Tco clkB is the clock-to-output delay of the clock buffer, Tflt clkB the propagation delay of

the signal traveling on the PCB trace from the clock chip to the driving component, Tco data

the clock-to-output circuit delay of the driver, and Tflt data the propagation delay of the PCB

trace from the driver to the receiver.

Now let's examine the total delay of the clock path to the receiver referenced to the first clock edge. This delay is represented by the solid lines on the right-hand side of the setup loop in Figure 8.2. The delay is shown as

(8.2)

where Tcycle is the cycle time or period of the clock, Tco clkA the clock-to-output delay of the

clock buffer, Tflt clkA the propagation delay of the signal traveling on the PCB trace from the

clock chip to the receiving component, and Tjitter the cycle-to-cycle period variation. The jitter

term is chosen to be negative because it produces the worst-case setup margin, as will be evident in the final equation.

The timing margin is calculated by subtracting equation (8.1) from (8.2) and comparing the difference to the setup time required for the receiver. The difference is the setup time margin:

(8.3)

To design a system, it is useful to break equation (8.3) into circuit and PCB delays, as in equations (8.4) through (8.8)

(8.4)

The output clock buffer skew is defined as (8.5)

This is usually specified in the component data sheet. The PCB flight-time skew for the clock traces is defined as

(8.6)

Subsequently, the most useful form of the setup margin equation is (8.7)

A common-clock design will function correctly only if the setup margin is greater than or equal to zero. The easiest way to compensate for a setup timing violation is to lengthen the clock trace for the receiver, shorten the clock trace to the driver, and/or shorten the data trace between the driver and receiver flip-flop.