Behavioural Modelling of Circuit Instance

The circuit instance graph defines the structure of the circuit instance at gate level. This subsection describes the propagation of transitions through the circuit instance during the application of a test vector-pair. Each node of the circuit instance is associated with a waveform, which consists of one or multiple transitions [Yalci97].

Definition 2.49 (transition). Atransition is an ordered pair τ= (v, t), where v∈ {0, 1} denotes the logic value after the transition and t ∈ R denotes the time at which the transition occurs.

Definition 2.50 (waveform). A waveform w is a non-empty list of transitions

w= ((v₀, t₀), ...,(v_m, t_m)), (2.71) such that t_k−1 <tk and vk−1 ̸=vk for all k∈N with 0<k≤m and w contains at least

the special transition (v₀, t₀) with t₀ = −∞, which defines the initial value v₀ of the waveform.

The initial value of a waveform is defined as the logic value set by the first transition in the waveform. Likewise, the final value of a waveform is defined by the last transition in the waveform.

The above definition of a waveform is an abstraction of the voltage waveforms obtained by SPICE simulations at electrical level. This abstraction provides a suitable trade-off between the accuracy and the complexity of statistical timing analysis.

The definition of the gate model at this higher abstraction level requires a formal foundation, which will be motivated by the example given infig. 1.4a. The figure shows that a transition at a gate input causes a transition at the gate output only after some delay. It is also visible, that the gate output voltage changes more rapidly in response to the rising transition at input ’b’ than in response to the falling transition at ’a’. This behaviour is described by this model at a higher abstraction level as follows. The arrival time t of a transition (v, t) at a circuit node describes the time at which the voltage crosses U_dd/2, where U_dddenotes the supply voltage. If a transition(v₁, t₁)at the input of a gate causes a transition (v₂, t₂)at the output of the gate, then the arrival time difference t₂−t₁ is called propagation delay. This is illustrated in fig. 2.6for an inverter (INV) with input ’i’ and output ’o’. The figure shows that the propagation delay is measured for a falling and a rising transition at the gate output and that these delays are different in general. It also defines the rise and fall time of a transition as the time between neighbouring 0.1U_dd and 0.9U_dd voltage crossing times.

q Figure 2.6 —Definition of propagation delay and rise and fall times [Rabae03] For primitive gates with two inputs, the gate delay also depends on which gate input is switching. This is due to the cell design but also because the slope of the gate input transitions depends on the circuit structure. For example, one of the gate inputs might be connected to a fanout-gate, that is, a gate whose output is connected to the inputs of multiple gate. As a consequence, the voltage at the gate input might change only very slowly, leading to higher propagation delay. Hence, in this model, each primitive gate with two inputs is associated with four propagation delay values, depending on which gate input is switching and if the transition at the gate output is a rising or falling transition.

For the complex cells XOR/XNOR, the propagation delay also depends on the logic values at the other gate inputs at the arrival time of the input transition. This is again due to the cell design and the circuit structure. Hence, each XOR/XNOR cell with two inputs is associated with eight delay values. From among these delay values, the appropriate value is selected for each input transition depending on the input at which the transition occurs, the state of the other gate input and the direction of the output transition created by the input transition.

A physical gate can only propagate a subset of the transitions at the gate inputs to the gate output. A transition (v, t) at one of the input nodes of a gate is propagated to the gate output node if and only if (v, t)satisfies the dynamic sensitization condition and the inertial delay condition. The conjunction of dynamic sensitization and inertial delay condition is called propagation condition.

The dynamic sensitization condition is always satisfied for a gate with only a single input and for XOR/XNOR complex cells. For AND/NAND and OR/NOR gates with two inputs, the opposite gate input must have the non-controlling value at the time t. A gate input is said to have a controlling value if it determines the gate output logic value irrespective of the other input values. The logic complement of the controlling value is called non-controlling value. For example, for an OR and NOR gate the controlling value is ’1’ and the non-controlling value is ’0’.

The inertial delay condition captures the physical limitation that a real gate cannot produce arbitrary short glitches at the output, as shown insection 1.3.1. Without loss of generality, the following description assumes that the gate output has stabilized to logic ’0’ or logic ’1’ by the time the transition (v, t) occurs at one of the gate inputs. Furthermore, it is assumed that (v, t) satisfies the dynamic sensitization condition so that the gate can propagate this transition to the gate output after a particular propagation delay δ. This delay represents the time the gate requires to charge or discharge the capacitive load connected to the gate output. The transition can only appear at the gate output if no other transition (v′, t′), which also satisfies the dynamic sensitization condition, occurs at the gate inputs during this time. More precisely, if there exists an input transition (v′, t′)that satisfies the dynamic sensitization condition of the gate and t < t′ < t+δ, then the inertial delay condition is violated by (v, t) and (v′, t′). Otherwise, (v, t)satisfies the inertial delay condition of the gate and is propagated to the gate output after delay δ.

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3

State of the Art

This chapter discusses the state of the art in fundamental statistical timing analysis problems that arise in delay test applications under the impact of delay variability. Recent methods that can be used for the variation-aware evaluation of path delay fault tests are discussed in section 3.1. The latest advances in the evaluation of the small delay fault tests and their limitation are reviewed in section 3.2. The normal distribution based SUM and MAX-operations are presented in section 3.3.1. Finally, recent approaches to improve the efficiency of the statistical SUM and MAX-operations are summarized in section 3.3.3.

3.1 Evaluation of Path Delay Fault Tests

This section summarizes previous methods, which can be used to analyse the sensitiza- tion of a path by a set of test vector-pairs under the impact of delay variations.