Assembly drawing
5.2 Data board
5.2.2 Board composition
Function
The analog part:
Conditioning and converting power
Monitoring voltage (including power voltage, WBC aperture voltage, RBC aperture voltage and FS background voltage, also monitoring laser drive current and AD working status, etc.)
Collecting and conditioning WBC/RBC volume signals
Detecting and amplifying HGB signals
Conditioning WBC DIFF signals
Driving constant-current supply
Controlling and setting amplification factors for all channels
Zapping apertures
AD conversion
The digital part:
Providing a platform for software operating
Controlling interfaces for the indicator board and the key board
Providing communication interfaces for the autoloader board and the drive board
Providing communication interfaces for PC
Controlling and monitoring interfaces for the volumetric board and the laser board
Processing digital signals and identifying pulse
Block diagram
Figure 5-6 Data board circuit
Analog power filter module
Monitoring module RBC/PLT amplification
HGB amplification
HGB led constant current driver Constant current source/zapping control module of RBC/PLT hole
Digital Constant current source /burn control
Power for analog circuits
WBC amplification
Constant current source/zapping control module of WBC hole
RBC／PLT
WBC aperture
FS base currrent signal monitoring of laser current driver
Constant current source /zapping control
Figure 5-8 Functions of digital part on data board
Description
The analog part:
Conditioning and converting voltages
The A±12V and AC120V analog power sent from the mother board are conditioned or converted to be the required voltages for the board. The AC120V is used for zapping apertures.
Monitoring voltage
The voltage of A±12V power and VCONST, WBC aperture voltage, RBC aperture voltage, FS blank voltage, laser drive current and AD working status are all monitored via AD.
Collecting and amplifying WBC/RBC volume signals
WBC/RBC volume signals are collected and conditioned, and then sent to the AD converter.
Detecting and amplifying HGB signals
The HGB current signals are converted into voltage signals through colorimetric method, then after conditioning, they are sent to the AD converter.
Conditioning WBC DIFF signals
The WBC DIFF signals （including FS, SS and SF signal; SF signal reserved ）are first collected and conditioned, and then sent to the AD converter.
Driving constant-current supply
The data board provides the constant current for the electrodes of the WBC bath and the RBC/PLT bath and the HGB light.
The zapping voltage on-off, constant current supply/zapping switch and HGB light on-off are controlled by the GPIO interface of CPU. The amplification factors of WBC DIFF, WBC, RBC/PLT and HGB signal channels are set by the FPGA as required.
Zapping aperture
If the analyzer has been running for a certain period or the WBC/RBC bath aperture clogs, the zapping function shall be performed to clean up the aperture by high temperature.
A／D conversion
The cell signals (WBC, RBC, PLT and WBC DIFF signals), voltage monitoring signals and HGB signals are converted into digital signals, and then sent to FPGA for further processing.
The digital part:
Providing a platform for operating system and application software CPU： MCF5474, 266MHz；
DDR：128M, 133MHz；
FLASH：16Mx16bit
Communicating with the TTL port of the driver board
Sending control command to the driver board and receiving its response.
Baud rate: 38400bps Data bit: 8bit
Stop bit: 1bit Start bit: 1bit Parity: even
Communicating with the 422 port of the autoloader board
Sending control command to the autoloader board via serial port and receiving its response.
Baud rate: 38400bps Data bit: 8bit
Stop bit: 1bit Start bit: 1bit Parity: even
The IO port for the driver board and autoloader board upgrading
By simulating the JTAG sequence through the CPU IO port, the driver board and the autoloader board can be upgraded respectively.
Interface for the indicator board
The status indicator and the buzzer on the indicator board are controlled by the CPU IO port.
Interface for the volumetric board
Status detection interface
Detecting the open/closed status of the side door and laser shielding box
Analog signal input interface
Receiving the analog signals from the pre-amplification board and the aperture electrodes
10M／100M network interface
The network interface is introduced by the mother board and connected to PC by the cross network cable, and capable of program downloading and data transmission, etc.
BDM debug interface
The BDM interface of CPU, which is used for detecting hardware, downloading program and writing the FLASH, is not available for customers.
JTAG interface of FPGA
It debugs FPGA and downloads FPGA program. It is not available for customers.
Interface definition
The data board is a plug-in board. It provides 9 connectors: the connectors for aperture electrodes, the connector to connect the digital part to the mother board, the connector to connect the analog part to the mother board, the connectors for debugging and the reserved connectors. See Figure 5-9 for the layout of the data board.
See the following table for the function of each connector.
Table 5-46 Interfaces of data board
Connector Function Number of
pins Note
J1 Connects the RBC/PLT aperture
electrode 3 /
J2 Connects the WBC aperture electrode 3 / J3 Connects the digital part to the mother
board 96 /
J7 Connects the analog part to the
mother board 96 /
The layout of interfaces is shown in the figure below:
Figure 5-9 Interfaces layout of data board
Definition of J1
J1 is the signal interface of RBC/PLT.
Table 5-47 Definition of J1
Pin Name Note
1 SHELL Shielding ground
2 RHOLE_A RBC/PLT signals
3 RHOLE_B RBC analog ground
Definition of J2
J2 is the signal interface of WBC.
Table 5-48 Definition of J2
Pin Name Note
1 WHOLE _B WBC analog ground
2 WHOLE_A WBC signals
3 SHELL Shielding ground
Table 5-49 Definition of J3
Pin Definition Function Pin Definition Function A1 D+5V Power supply B17 JTAG_TCK_
AS
JTAG clock of autoloader board
A2 D+5V Power supply B18 JTAG_TO_A S
JTAG sending of autoloader board
A3 D+5V Power supply B19 JTAG_FROM _AS
JTAG receiving of autoloader board
A4 D+5V Power supply B20 UART1_TO_
DAT+
Reserved debug serial port sending
A5 D+5V Power supply B21 UART1_TO_
DAT-
Reserved debug serial port sending
A6 DGND Signal ground B22 DGND Signal ground A7 DGND Signal ground B23 DGND Signal ground A8 DGND Signal ground B24 DGND Signal ground
A9 DGND Signal ground B25 #VMCTRL Volumetric board enabling A10 DGND Signal ground B26 #RBC_STAR
T
Start RBC volume metering
A11 DGND Signal ground B27 #RBC_STOP Stop RBC volume metering
A12 TP_TX+ Positive sending terminal of network
B28 #WBC_STAR T
Start WBC volume metering
A13 TP_TX- Negative sending terminal of network
B29 #RBC_STOP Stop WBC volume
metering
A14 DGND Signal ground B30 DGND Signal ground A15 DGND Signal ground B31 #LASER_CT
RL
Laser board enabling
A16 JTAG_TMS JTAG mode signal
B32 DGND Signal ground
A17 JTAG_TCK JTAG clock signal C1 D+5V Power supply A18 JTAG_TO_
DRV
JTAG sending of drive board
C2 D+5V Power supply
A19 JTAG_TO_
DAT
JTAG receiving of drive board
C3 D+5V Power supply
A20 DGND Signal ground C4 D+5V Power supply A21 DGND Signal ground C5 D+5V Power supply A22 UART0_TO Serial port C6 DGND Signal ground
_DRV sending of drive board
A23 UART0_TO _DAT
Serial port receiving of drive board
A28 DGND Signal ground C12 TP_RX+ Positive receiving terminal of network
A29 DGND Signal ground C13 TP_RX- Negative receiving terminal of network
A30 DGND Signal ground C14 DGND Signal ground A31 DGND Signal ground C15 DGND Signal ground A32 DGND Signal ground C16 UART3_TO_
PC
PC communication serial port sending
B1 D+5V Power supply C17 UART3_TO_
DAT
PC communication serial port receiving
B2 D+5V Power supply C18 DGND Signal ground B3 D+5V Power supply C19 DGND Signal ground B4 D+5V Power supply C20 UART1_TO_
AS+
autoloader board serial port sending
B5 D+5V Power supply C21 UART1_TO_
AS-
autoloader board serial port receiving B10 DGND Signal ground C26 ＃BUZ Buzzer control output B11 DGND Signal ground C27 #COUNT_KE
Y
Aspirate key control input
B12 PWFBOUT Network power C28 FAULT_J Indicator control output
B15 DGND Signal ground C31 #RIGHT_DO OR
Right door status monitoring input
Compartment door open key control input
Definition of J7
J7 is the signal interface for the analog part of data board and mother board, and is European 96 pin plug.
Table 5-50 Definition of J7
Pin Name Note Pin Name Note
A14 AGND Analog ground B30 AC120V_
B
Zapping voltage input
A15 AGND Analog ground B31 NC /
A26 NC / C10 AGND Analog ground
Zapping voltage input C16 AGND Analog ground
B1 AGND Analog ground C17 AGND Analog ground
J8 is the JTAG interface of FPGA.
Table 5-51 Definition of J8
Pin Name Note
1 FPGA_TCK Clock
2 GND Signal ground
3 FPGA_TDO Data output
4 VDD Power supply
9 FPGA_TDI Data input
10 GND Signal ground
Definition of J9
Reserved. Not available for customers.
Definition of J10
Reserved. Not available for customers..
Definition of J11
Reserved. Not available for customers.
Definition of J13
J11 is the BDM interface of CPU.
Table 5-52 Definition of J13
Pin Definition Function
1 NC /
2 BKPT# Breakpoint setup
3 GND Signal ground
4 DSCLK synchronizing clock input
5 GND Signal ground
24 PSTCLK Processor clock
25 NC /
26 MCF_TA# Transmission response
Assembly drawing
Figure 5-10 Assembly drawing of data board
5.2.3 Adjustment and Test Points
All the adjustable parameters of analog part are adjusted as per the command of FPGA. Adjust the parameters' settings in the software interface if necessary.