BUS-BASED DYNAMIC INTERCONNECTION NETWORKS 1 Single Bus Systems

A single bus is considered the simplest way to connect multiprocessor systems. Figure 2.2 shows an illustration of a single bus system. In its general form, such a system consists of N processors, each having its own cache, connected by a

Figure 2.1 A topology-based taxonomy for interconnection networks.

shared bus. The use of local caches reduces the processor – memory traffic. All pro- cessors communicate with a single shared memory. The typical size of such a system varies between 2 and 50 processors. The actual size is determined by the traffic per processor and the bus bandwidth (defined as the maximum rate at which the bus can propagate data once transmission has started). The single bus network complexity, measured in terms of the number of buses used, isO(1), while the time complexity, measured in terms of the amount of input to output delay isO(N).

Although simple and easy to expand, single bus multiprocessors are inherently limited by the bandwidth of the bus and the fact that only one processor can access the bus, and in turn only one memory access can take place at any given time. The characteristics of some commercially available single bus computers are summarized in Table 2.1.

2.2.2 Multiple Bus Systems

The use of multiple buses to connect multiple processors is a natural extension to the single shared bus system. A multiple bus multiprocessor system uses several parallel buses to interconnect multiple processors and multiple memory modules. A number of connection schemes are possible in this case. Among the possibilities are the multiple bus with full bus – memory connection (MBFBMC), multiple bus with single bus memory connection (MBSBMC), multiple bus with partial bus – memory connection (MBPBMC), and multiple bus with class-based memory connection (MBCBMC). Illustrations of these connection schemes for the case of N¼6 processors, M¼4 memory modules, and B¼4 buses are shown in Figure 2.3. The multiple bus with full bus – memory connection has all memory modules connected to all buses. The multiple bus with single bus – memory connec- tion has each memory module connected to a specific bus. The multiple bus with partial bus – memory connection has each memory module connected to a subset of buses. The multiple bus with class-based memory connection has memory mod- ules grouped into classes whereby each class is connected to a specific subset of buses. A class is just an arbitrary collection of memory modules.

One can characterize those connections using the number of connections required and the load on each bus as shown in Table 2.2. In this table, k represents the number of classes;grepresents the number of buses per group, andMjrepresents the number of memory modules in classj.

TABLE 2.1 Characteristics of Some Commercially Available Single Bus Systems

Machine Name Maximum No. of Processors Processor Clock Rate Maximum Memory Bandwidth HP 9000 K640 4 PA-8000 180 MHz 4,096 MB 960 MB/s IBM RS/6000 R40 8 PowerPC 604 112 MHz 2,048 MB 1,800 MB/s

In general, multiple bus multiprocessor organization offers a number of desirable features such as high reliability and ease of incremental growth. A single bus failure will leave (B21) distinct fault-free paths between the processors and the memory modules. On the other hand, when the number of buses is less than the number of memory modules (or the number of processors), bus contention is expected to increase. P P P P P P M M M M a P P P P P P M M M M b c

Figure 2.3 (a) Multiple bus with full bus – memory connection (MBFBMC); (b) multiple bus with single bus-memory connection (MBSBMC); (c) multiple bus with partial bus – memory connection (MBPBMC); and (d) multiple bus with class-based memory connection (MBCBMC).

2.2.3 Bus Synchronization

A bus can be classified as synchronous orasynchronous. The time for any trans- action over a synchronous bus is known in advance. In accepting and/or generating information over the bus, devices take the transaction time into account. Asynchro- nous bus, on the other hand, depends on the availability of data and the readiness of devices to initiate bus transactions.

In a single bus multiprocessor system, bus arbitration is required in order to resolve the bus contention that takes place when more than one processor competes to access the bus. In this case, processors that want to use the bus submit their requests to bus arbitration logic. The latter decides, using a certain priority scheme, which processor will be granted access to the bus during a certain time interval (bus master). The process of passing bus mastership from one processor to another is calledhandshaking and requires the use of two control signals:bus requestandbus grant. The first indicates that a given processor is requesting master- ship of the bus, while the second indicates that bus mastership is granted. A third signal, calledbus busy, is usually used to indicate whether or not the bus is currently being used. Figure 2.4 illustrates such a system.

In deciding which processor gains control of the bus, the bus arbitration logic uses a predefined priority scheme. Among the priority schemes used are random

d

Figure 2.3 Continued.

TABLE 2.2 Characteristics of Multiple Bus Architectures

Connection Type No. of Connections Load on Busi

MBFBMC B(NþM) NþM MBSBMC BNþM NþMj MBPBMC B(NþM/g) NþM/g MBCBMC BNþPk_j¼1Mj(jþBk) Nþ P_k j¼max (iþkB,1)Mj, 1iB

priority, simple rotating priority, equal priority, and least recently used (LRU) pri- ority. After each arbitration cycle, in simple rotating priority, all priority levels are reduced one place, with the lowest priority processor taking the highest priority. In equal priority, when two or more requests are made, there is equal chance of any one request being processed. In the LRU algorithm, the highest priority is given to the processor that has not used the bus for the longest time.