It is desirable to describe some basic features of the CAD software used in this work for the design of the digital logic circuit, although it is a very brief description. User configurable logic devices combine the logistical advantages of fixed integrated circuits with the architectural flexibihty of custom devices. These programmable de-
vices allow the designer to electrically programme standard logic elements to meet the specific need of each apphcation. This allows computer design and fabrication w ithout the costs and lengthy times related to building custom integrated circuits. A ltera’s EPLDs range in density from a few hundred to several thousands of equiva lent gates allowing cost effective implementation of TTL functions onto a minimum board area without drawbacks of custom circuits [2].
The EPLDs are created using CMOS EPROM (Erasable Programming Read Only Memory) technology. Their architecture is explained more fully in User Manual [2]. The CAD development software system associated with these EPLDs runs on an IBM PC clone and is used in conjunction with hardware modules in order to pro gramme the EPLDs with the logic produced. Before it is programmed, the logic can be tested using software simulation. This ability to test the logic before hardware programming is a very useful facihty of the system. The recently-upgraded software package offers graphical timing diagrams to analyse the simulation results.
One of the main advantages in EPLD design approach is th at the chip count for a controller design can be minimised to only a few components. It is possible to design a digital circuit for a mosaic CCD controller with a total of 2 digital devices (one EPLD, one memory chip) plus a system clock and buffers, in principle. This is im portant to deal with an indefinite sensing area [i.e. many CCDs) as the long term goal, and particularly to accommodate the digital circuits in the cryostat by minimising the circuit areas for low noise performance. The analog circuits can also be minimised by using surface mount devices. The fast system clock rate is another advantage of this approach. The clock rate of microprocessor based design (or transputer approach) is about 20 MHz, at most [106], [28], whilst the fastest clock rate obtainable with the EPLD design is 80 MHz (in the case of EPM 7256). This implies th at more CCDs can be driven by multiplexing the waveforms within a given period of time.
The EPLD based architecture does not lack the design flexibihty of microprocessor based controllers. A EPLD based design can be easily upgraded w ith the CAD software, and programmed chips can be easily erased to implement another design. Further, timing delays of the design are predictable by software simulation. The advantages of using the EPLD CAD software in designing the system may be sum-
marised as follows.
• Compactness : Up to 20 thousand logic gates can be integrated in a single EPLD device. This can contribute to lower the chip count compared to a microprocessor based design for the same purpose.
• Flexibility : Modification or upgrade of a design, e.g. for a completely different CCD architecture, is possible if necessary. The old design programmed into a EPLD can be erased, and a new design can be reprogrammed into the chip. For all normal optimisation of devices, only the Bitmap would of course need to be changed.
• Low cost and easy handhng : It could be more economical than using many discrete TTL devices for the equivalent circuit. A digital circuit can be easily implemented with minimal hardware work, such aa soldering or PCB process ing. Chances of malfunction can be reduced compared to a design with many discrete TTL devices.
• Timing delays of the design are predictable since the EPLD is not subject to any instruction or interrupted time overhead compared w ith microprocessors, and does not require any low level-language programming.
• Simulation ability : Any circuit design can be verified by simulation with graphical timing waveforms before it is programmed, and the simulation result is reflected exactly in actual performance.
• Simple system control software : Due to its simple hardware architecture, the system control software can be simpHfied compared to a microprocessor based software.
e Easy to copy : The design can be programmed into as many EPLDs as we need. No hardware work is necessary to produce the same circuitry.
Throughout this work, two versions of the EPLD CAD software have been used. Most of digital logic designs of this chapter have been created by the MAX-fPLUS (Multiple Array m atriX Programmable Logic User System) CAD software system which is the recent version of the A ltera company. The earlier version, A-I-PLUS
DESIGN E N T R Y Hierarchical AHD L Files B oolean E q u a tio n s T r u th T a b le s H ierarchical S c h e m a t i c s .A D F o r .S M F D o c u m e n ts DESIGN P R O C E S S IN G
EPLD
S IM U LA TIO NDESIGN VERIFICA TIO N A D F 2 C N F F itte r Logic S y n th e s is A sse m b le r Logic M inim iser S im u la to r P r o g r a m m in g S o f tw a r e & H a rd w a r e M A X + P L U S T e x t E d itor W a v e fo r m E ditor M A X + P L U S G ra p h ic E ditor S u p e rv iso r & D a ta b a s e M a n a g e r
A ltera Programmable Logic User System), has been used to design the 48 bit De m ultiplexer Latch th at distributes the digital drive waveforms for each CCD. Except for this, the A-fPLUS haa been employed only for the design of the initial developing stage circuits until the MAX-fPLUS version was released. MAX-j-PLUS can handle up to 20 thousands logic elements in a single chip and offers graphic waveform edit ing facihties to analyse the simulation results. The structure of this software system and associated utiHties are schematically shown in Figure 3.2 [1].
In fact, MAX+PLUS is a combination of hardware and software which allows circuit designers to develop and implement custom logic circuits providing rehable hard ware chips very conveniently. This software was installed on an IBM 386 compatible PC with an Intel 80387 m ath co-processor. It was used with a Mouse in conjunc tion w ith a Programming Unit and a Programming Circuit Board to produce the EPLDs. Appendix B presents a brief description of this software utiHty, and further explanations can be found in related user references [1], [2], [3].
Using the facihties of the software system shown in Appendix B, a digital logic circuit design can be conveniently implemented into an actual working siHcon hardware w ith its functional testing and related timing performance evaluation. However it is not always easy to obtain the required circuit design with correct simulation results to be programmed into a device. This is not only because it needs skilful m anipulation of compHcated software but also proper use of available resources of a chosen EPLD such as internal assignments of macrocells (more detail in Appendix B) or pin arrangements of a given circuit. Selection of a suitable EPLD device for a given circuitry is another im portant factor. The general sequence to design a circuit is also described very briefly in Appendix B.
3.3
C ontroller B oard D esig n
3.3.1
O verview
This section presents descriptions of the digital design for the mosaic CCD controller which can drive many CCDs simultaneously. Initially the design is aimed at driving four CCDs. However, as far as the digital design is concerned, it can easily deal with
a larger number of CCDs, th at is up to 32, with only a few modifications depending on associated software and the analog circuitry. Hereafter, the exact meaning of the
Controller of this work is defined as the digital circuitry that generates the entire sequences of digital waveforms which are needed to readout the integrated charge on the CCDs. It also includes relevant signals to interface with a computer and system control signals. This is a rather narrow meaning, reminding th at the term ‘controller’ is often used to mean the whole CCD electronics.
There axe many methods to provide proper drive waveforms for reading out the integrated charge on the CCDs. McLean [86] has extensively described possible methods to control the CCDs which can be classified into two categories in gen eral. The first one is based on the hardwired system meaning th a t the electronic functions are carried out by circuitry and cannot altered by typing instructions on a computer keyboard. Meanwhile the other is based on program m able designs such th a t electronic functions can be controlled by computer commands. In this work, the circuit has been designed to allow adjustm ent of as many system param eters as possible by the software. As an example, the number of pulses together with their timing and phase, the number of CCDs to be controlled and its clocking sequences can be arranged by the software with a computer. Therefore the design of this work can be classified as the latter case. This kind of approach requires the use of mem ory devices which can store the necessary information for required drive waveform sequences.
In fact the basic concept of a controller circuitry of this work can be characterised as a memory device control circuit. The information stored in the memory device is w ritten by the software as a form of Bitmap, which represents the specific instruc tions for timing waveforms. A Bitmap is defined as a series o f logical O^s and 1 ’s in controller memory devices which specifies the Low and High o f the CCD clocks.
The Bitmap, comprising many O’s with a few I ’s, defines events.
The sequences of digital drive waveform which is apphcable to most kinds of CCDs, can be defined as a form of a Bitmap, and generated by a proper circuitry, for example a sequence of one vertical clocking followed by a horizontal clocking, etc. The most im portant part of the design is the logic circuit which controls memory addresses during downloading a Bitmap from software or reading it out from memory devices.
C O N T R O L L E R B O A R D C o n tro l Bus A d d re ss D a ta ( B i t m a p ) S y s te m Clock E P L D C o n tro lle r C o n tro l C o m p u te r M e m o ry
A n a lo g Driver B oard Digital W a v e f o r m
Figure 3.3: The controller design concept.
After writing the Bitmap into the memory devices, cycling round the memory can generate the digital waveform directly. Many of the system param eters such as the num ber of pixels and lines can also be given as input data to the hardw are by a user. In this work, the hardware for such digital controller circuitry has also been made by CAD software, and contained in a single EPLD chip. The concept for the controller design is shown in Figure 3.3.