Cache Coherence Property

The cache memory is coherent if it maintains one of the cache coherence protocols such as MSI, MESI, MOESI and many others [213]. The MSI Protocol is chosen because it is simple, and it serves the purpose. In section5.2.2I have covered the protocol and explained the meaning of the states the protocol indicates such as Modified, Shared and Invalid. Each state is shortened to one capital letter “M” for Modified, “S” for Shared, and “I” for Invalid. The following table, Table ??, describes the allowed and forbidden occurrences of these MSI states of the cache memory in multi-core architecture:

Table 6.1: MSI Protocol

Modified Shared Invalid

Modified 7 7 3

Shared _{7 3 3}

Invalid _{3 3 3}

This criteria is applicable on at least two entities or more. The Modified state “M” is highly restricted, and it does not accept any other states but Invalid “I”. The Shared state “S” is less restricted; it accepts another cache block to be either Shared “S” or Invalid “I”. The Invalid state “I” is tolerating, and it accepts all three states Modified “M”, Shared “S” or Invalid “I”.

Cache coherence can be achieved by maintaining MSI Protocol. This correctness property can be expressed formally in Interval Temporal Logic (ITL) as follows:

` MSI Protocol[X,Y] = (State[X][Index] = M odif ied ∧ State[Y ][Index] = Invalid) ∨ (State[X][Index] = Shared ∧ (State[Y ][Index] = Shared ∨ State[Y ][Index] = Invalid)) ∨ (State[X][Index] = Invalid ∧ (State[Y ][Index] = M odif ied ∨ State[Y ][Index] = Shared ∨

The formula expresses the allowed the MSI Protocol of two cache blocks for processors X and Y . When the MSI Protocol states meet this formula, then the correctness property of the cache coherence is satisfied.

The acronym of MSI Protocol states “M”, “S” and “I” are replaced by “1”, “2” and “3” respectively in MATLAB graphs in order to be able to plot them as integer values of y-axis, while x-axis represents the processors identification P id0,1,2.

STATE 0: By referring to Figures 6.7 & 6.8, it can be seen that processor P id1 modifies

cache block 6 by writing data 25 to it, so it becomes Modified Cache[1][6] = 25 because the main memory is not updated yet and no other cache blocks share this new data. The same cache blocks of processors P id0 & P id2 are still empty, and are, therefore, Invalid. See Figure6.21

STATE 1: Processor P id1 writes a new data to the same cache index 6 which is written to

in the previous state. The data is 0, Cache[1][6] = 0, MSI state of this cache index is Modified as neither the main memory nor the other cache blocks hold the new written data. The other processors P id0 & P id2 are still Invalid. See Figure6.22

STATE 2: Processor P id2 requests to read the main memory address 2. Cache index 2 of

processor 2 Cache[2][2] = −16 and the main memory of address 2 M emory[2] = −16 share the same data. Therefore, the MSI protocol of Cache[2][2] is Shared, while the other processors are still empty, which means that their MSI states are Invalid. See Figure6.23

STATE 3: Cache index 0 of processor 2 Cache[2][0] is Modified because a write request is made. The data in main memory of the correspondent address is different from this cache index. The other processors P id0 & P id1 are empty, therefore, their MSI state are Invalid. See Figure

6.24

STATE 4: Processor P id0 requests to read a correspondent cache index 7 of the requested

address 15, Cache[0][7]. The main memory M emory = −16 fetches its data to this cache index. Therefore, the MSI state of this cache block is Shared as it is consistent with the main memory data. The other processors are empty, and their MSI states are Invalid. See Figure6.25

STATE 5: Processor P id2 requests to read address 0, because this address has recently been

in state 3 and received a write request of data 0 to it. Therefore, at this state the requested read address returns 0, Cache[2][0] = 0. The MSI state is still Modified because the correspondent address in the main memory holds different data. The other processors, P id0& P id1, are Invalid.

STATE6: Cache block 4 of processor 1 holds data -16 after it is fetched by the main memory of address 4 as a consequent of the read request initialised by P id1. Therefore, Cache[1][4] =

−16 which means that the MSI state of this cache block is Shared. Because the other processors P id2& P id0are still empty, their MSI states are Invalid. See Figure6.27

STATE7: Processor P id2requests to write data 23 to cache index 4, so it becomes Cache[2][4] =

23. This cache block of P id2was Invalid in the previous state because it was empty. At this state,

it becomes Modified as it has just received a new data while the main memory of the correspon- dent address is still not updated. Processor P id1 changes its cache block from being Shared at

the previous state to Invalid at this state. Processor P id0is still empty, therefore, it is Invalid too.

STATE 8: Processor P id2 requests to read cache index 5 and because this cache block is

empty, the main memory of address 5 fetches its data, M emory[5] = −16 to it. The cache memory of processor 2 becomes Cache[2][5] = −16, which means it is in the Shared MSI state. Processors P id0 & P id1 are still empty, which means that their MSI states are Invalid.

STATE 9: Processor P id1 requests to read cache index 1, and because this cache block is

empty, the main memory of address 9 fetches its data, M emory[9] = −16 to this cache block, so it becomes Cache[1][1] = −16. Therefore, this cache block has Shared MSI state while the other processors, P id0& P id2, have Invalid MSI states. See Figure6.30