Here, we briefly review aspects of the C I arbi tration related to the performance study. Refer ence 1 contains details of the CI bus arbitration .
Digital Teclmical]ournal
No. 5 Septem ber 1987
A Simple Description of a CI Bus
Let us assume a VAXcluster system in which there are N nodes attached to a CI bus. Each node can send both information and acknowledge packets through the bus to any other node. Upon receiv ing an information packet, a node first checks the cyclica l redundancy check (CRC) information in that packet. If the CRC succeeds, the receiving node will immediately send back to the transmit ting node an acknowledge packet with either an acknowledgment (ACK) if the node accepts and stores the packet correctly, or a non-acknowledg ment (NAK) if not. If the CRC fai ls, the node will send no response .
A time period, called the quiet slot, is reserved to guarantee the transmission of the acknowledge packet. The quiet slot (QS) is defined as the period of time needed to accommodate the time delay through a node's front-end logic, plus the round-trip cable and coupler delays for the longest path in a CI c luster installation . Only the node that generates the acknowledge packet for the i nformation packet just received can grasp the CI bus during the quiet slot fol lowing the transmission of any information packet. Thus, as an approxi mation, the transmission time of the information packet may be extended to incl ude the transmission time of the acknowledge packet. After sending an information packet, the trans m i tting node wai ts for the length of an acknowl edge time-out period. If that node receives an ACK during that period , the transm it is com pleted . Upon receiving a NAK or no response within the time-out period , however, the trans-
Cl Bus Arbitration Performance in a VAXcluster System
mitting node must retransmit the packet. The acknowledge time-out period is greater than the sum of one quiet slot , plus the CI bus turnaround time, plus the time to verify and accept the acknowledge packet at the transmitting node .
In addition, in any such "shared" multinode bus structure, the arbitration for use of the bus so as to avoid col lisions is a critical element of the design . The CI bus architecture implements the distributed arbitration scheme d iscussed below.
CJ Bus A rbitration
Two identical Cl paths are used in a VAXcluster system, and all nodes are connected to both of them. Each node can randomly pick one path before transmi tting an information packet. Once having chosen a path, the node will use it until an acknowledge packet from the destination node has been received. However, each node cannot transmit and receive simultaneously using two different paths. Figure 1 illustrates the structure of a VAXcl uster system in which VAX CPUs and HSC devices are connected to one CI pat h .
Arbitration must b e performed by all nodes prior to the transmission of any information packet. The acknowledge packet, following re ceipt of an information packet, does not require arbitration. This method is called a slotted-carrier sense multiple access (CSMA) protocol, a lso referred to as dual-count round robin. The fol lowing parameters are used in current VAXclus ter systems :
• The clock u n i t (TCLK) is s e t a t 1 1 4 . 2 8 nano seconds ( ns) .
• The va lue of the quiet slot can range from 7 to
64 TCLKs, or 800 to 7 , 3 1 4 ns, depending on the cable length of the cluster. The QS for the for the discussion of this paper simulation is
1 , 1 4 3 ns. 94 HSC i + 1 DISKS . . . HSC n DISKS
Figure 1 A Typical VAX cluster System
• The maxi mum number of nodes in the cluster,
N, is 1 6 for the current algorithmic implemen tation .
• The IO numbers of the nodes are 1 = 0 ,
1 , . . . , N -1, one for each node .
The arbi tration a lgorithm operates as follows:
1 . Upon starting a transmit operation , node I
chooses randomly one of the C I paths and sets the value of i ts arbitration counter, C, to
N + l + l .
2 . I n each TCLK period , the node determ ines whether or not the C I bus is busy. If i t is busy, the arbitration counter will remain unchanged .
3 . Once the node senses that the CI bus is not busy, it will start counting quiet slots. That is, the arbitration counter is set to C - 1 , and the node then wai ts for one QS period . If C > 0 at the end of one QS period , the node wil l inquire if the CI bus is busy. If i t isn ' t busy, C i s set t o C -1 , and the node waits during one additional QS period . lf the CI bus is busy, the arbitration counter is set to another va lue that depends on the node I D .
• I f the C l bus is occupied by a node whose I D is greater than I, or if this is the node's first attempt to grasp the CI bus, then C is set to N + I + 1 ( i . e . , the initial value of C for this node) .
• I f the CI bus is occupied by a node whose
1 0 is less than I and this is not the first attempt of node I to grasp the CI bus, then C is set tO
I +
1 . After the arbitra tion coun ter is reset, control returns tO step 2above.
If C = 0 at the end of the QS period , the node
inquires again if the CI bus is busy. If so, the arbitration counter is set to another value that depends on the node 10, as explained just above . I f the CI bus is not busy, the node inquires if a packet is being received from t he other path.
• I f the node is receiving from the other path, C is reset to N, and control goes to step 2 above .
• If the node is not receiving, it starts the
transmission i mmediately.
Digital Tecbtzical]om-nal