8.4 Future Work
8.4.5 Beyond Circuit Analysis
The reason for creating a circuit analysis system was to enable chip designers to create more reliable microchips by highlighting areas susceptible to the issues of electromigration and IR drop. However, these are not the only types of problem that can cause chip unreliability, there are other issues such as failures in the logic can that cause a chip to behave unexpectedly.
Therefore, the system could be expanded to include testing of the logic of a chip design. Implementing this would require extensive research into how logic is implemented in a circuit and how to test that if it will work correctly.
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Appendix A
Example ring and mesh from an IC design in Lyric
Figure A.1: The thick track that runs around the outside of the gridded area is known as a ring. It is a track of metal that supplies power. The gridded area is known as a mesh. It is a grid of wires that delivers power from the ring to the cells beneath it.
Appendix B Screenshots
Figure B.1: Circuit analysis in Lyric
Figure B.2: Colouring of the branches after circuit analysis
Figure B.3: The Lyric toolbar
Figure B.4: The Lyric command line displaying the results of the circuit analysis
Appendix C
Be easy to use Allow staff at Pulsic to use the system and give feedback
Pulsic staff should be able
to perform
analysis on a circuit and provide positive feedback
PASS
Be able to run on all the platforms that Pulsic sup-port
Run the system on various dif-ferent platforms, using the same chip design, and note the results
The system
should produce the same results on each of the platforms
PASS
Be reliable Use the system numerous times to see if any bugs occur
The system
should always finish cleanly without crashing
MARGINAL FAIL
Appendix D
Circuit Designs for Testing Purposes
D.1 Test Design 1
Figure D.1: This design has 10 nodes, with a 5 volt voltage supply at node 1, a 3 volt supply at node 3, a 4 volt supply at node 9 and a 5 amp current source at node 6. The resistance along each branch is 1 ohm.
D.2 Test Design 2
Figure D.2: This design has 9 nodes, with a 1 volt voltage supply at node 1 and a 1 amp current source at node 9. The resistance along each branch is 1 ohm.
Appendix E Test Results
E.1 System v PSpice using Test Design 1
This System PSpice 5.000000v 5.000v 3.624606v 3.625v 3.000000v 3.000v 3.949527v 3.950v 2.873817v 2.874v -0.078864v -0.0786v
1.968454v 1.968v 3.974763v 3.975v 4.000000v 4.000v 2.984227v 2.984v
E.2 System v PSpice using Test Design 2
This System PSpice 1.000000v 1.000v 0.500000v 0.500v 0.250000v 0.250v 0.500000v 0.500v 0.250000v 0.250v 0.000000v 0.000v 0.250000v 0.250v 0.000000v 0.000v -0.500000v -0.500v
E.3 Multiple Platform Testing using Test De-sign 1
Windows XP Pro Solaris 8 SuSE Linux 9.0 5.000000v 5.000000v 5.000000v 3.624606v 3.624606v 3.624606v 3.000000v 3.000000v 3.000000v 3.949527v 3.949527v 3.949527v 2.873817v 2.873817v 2.873817v -0.078864v -0.078864v -0.078864v 1.968454v 1.968454v 1.968454v 3.974763v 3.974763v 3.974763v 4.000000v 4.000000v 4.000000v 2.984227v 2.984227v 2.984227v
E.4 Multiple Platform Testing using Test De-sign 2
Windows XP Pro Solaris 8 SuSE Linux 9.0 1.000000v 1.000000v 1.000000v 0.500000v 0.500000v 0.500000v 0.250000v 0.250000v 0.250000v 0.500000v 0.500000v 0.500000v 0.250000v 0.250000v 0.250000v 0.000000v 0.000000v 0.000000v 0.250000v 0.250000v 0.250000v 0.000000v 0.000000v 0.000000v -0.500000v -0.500000v -0.500000v
Appendix F
Output Files from System Testing
F.1 Windows XP Pro using Test Design 1
¨ ¥
40
F.2 Windows XP Pro using Test Design 2
¨ ¥
7 node 4 , v o l t a g e = 3 . 9 4 9 5 2 7
23 r e s i s t o r 3 , c u r r e n t = 0 . 5 0 0 0 0 0
F.5 SuSE Linux 9.0 using Test Design 1
¨ ¥
43 r e s i s t o r 1 2 , c u r r e n t = 0 . 0 2 5 2 3 7
44
45 r e s i s t o r 1 3 , c u r r e n t = 1 . 0 1 5 7 7 3
§ ¦
F.6 SuSE Linux 9.0 using Test Design 2
¨ ¥
F.7 Diff of the Output Files of MNA and Iter-ative Algorithms
The following is a file containing the results of a diff on the files output by the MNA algorithm and the iterative algorithm after analysing a 40 node circuit.
This shows that the iterative algorithm has produced results.
¨ ¥
70 < r e s i s t o r 4 7 4 , c u r r e n t = 0 . 0 5 9 3 0 8
140 > r e s i s t o r 2 0 8 5 , c u r r e n t = 0 . 0 3 3 3 3 2
141 7448 c7448
142 < r e s i s t o r 2 1 2 4 , c u r r e n t = 0 . 0 2 0 7 1 1
143 −−−
144 > r e s i s t o r 2 1 2 4 , c u r r e n t = 0 . 0 2 0 2 2 4
145 7450 c7450
146 < r e s i s t o r 2 1 2 5 , c u r r e n t = 0 . 0 0 6 4 3 6
147 −−−
148 > r e s i s t o r 2 1 2 5 , c u r r e n t = 0 . 0 0 4 4 8 7
§ ¦
Appendix G
36 extern void updateNodeTable ( void ) ;
37
38 /∗ Hard coded example c i r c u i t f o r t e s t i n g p u r p o s e s ∗/
39 extern void example1 ( void ) ;
40
41 /∗ Hard coded example c i r c u i t f o r t e s t i n g p u r p o s e s ∗/
42 extern void example2 ( void ) ;
43
56 extern int printMenu ( void ) ;
57
43 {
113 {
181 {
249 {
315 }
385 i f ( node = ( node p ) m a l l o c ( s i z e o f ( n o d e t ) ) )
455 i f ( node = ( node p ) m a l l o c ( s i z e o f ( n o d e t ) ) )
525 }
595 r e s i s t o r −>i d = 1 1 ;
665 {
735 node−>r e s i s t o r s [ 2 ] = 7 ;
805 r T a b l e [ r e s i s t o r −>i d ] = r e s i s t o r ;
875 {
945 }
1015 int s t o r e ( void )
1085 p r i n t f ( ” Enter a r e s i s t o r i d t h a t t h i s node i s c o n n e c t e d t o \n” ) ;
1151
1220 // p r i n t f (”1 Enter c i r c u i t i n f o r m a t i o n manually \n ”) ;
20 Numerical R e c i p e s i n C: The Art o f S c i e n t i f i c Computing ,
90 }
160 putVal ( z , i , 1 , ( sum/ g e t V a l ( a , i , i , 1 ) ) , 1 ) ;
230 return 1 ;
300 M a t r i c e s are Ax = z
369 rows = v o l t a g e S o u r c e −>node ;
G.5 iterate.h
15 int changedB = 1 ;
82
149 w i t h t h e new r e s i s t a n c e . This i s done u s i n g Ohms law
214
247 newNodeList−>nodeID = r e s −>node2 ;
248
263 newNodeList−>nodeID = r e s −>node1 ;
264
278 /∗ Free t h e p r e v i o u s node s i n c e i t i s now u s e l e s s ∗/
340 node = nTable [ currentNode−>nodeID ] ;
341 node−>i n L i s t = 1 ;
342 curren tNode = currentNode−>next ;
343 }
344
345 /∗ Perform t h e a n a l y s i s on t h e nodes i n t h e l i s t ∗/
346 n o d e L i s t = a n a l y s e ( n o d e L i s t ) ;
416 p r i n t f ( ” E r r o r − c o u l d not f i n d r e s i s t o r %d i n r e s i s t o r t a b l e \n” ,
37 c u r r e n t = 0 . 0 − c u r r e n t ;
31
101 i f ( nTable [ count ] != NULL )
4 /∗ Function t o g e t a v a l u e from a p a r t i c u l a r e l e m e n t i n a m a t r i x ∗/
42 {
110 i f (A)
180 vSource = vTable [ count ] ;
53 } ;
12 #include ” output . h”
24 extern void example1 ( void ) ;
25 extern void example2 ( void ) ;
26 extern int s t o r e ( void ) ;
27 extern void u s e r I n p u t ( void ) ;
28 extern int printMenu ( void ) ;
29
82 }
151 }
38 extern void updateNodes ( void ) ;
39
58 /∗ Function t o r e t u r n c a l c u l a t e d e l e m e n t c u r r e n t ∗/
47
115 i f ( node )
G.17 Segment of code used to interface the
sys-tem with Lyric
7 #define BADVAL −1
77
144 e l s e
211 i f ( nodev>maxvolt ) maxvolt=nodev ;
280 int c u r s t y l e =−1;
330 TEXT ANCHOR CENTER, TEXT ORIENT AUTOMATIC, 0 , R FALSE ,
R FALSE) ;
346 }
347 }
348 }
349 }
350 }
351 /∗ }}} ∗/
352 }
353 /∗ }}} ∗/
354 #endif
355 }
§ ¦