DC CIRCUIT ANALYSIS OF INTEGRATED CIRCUITS FOR THE LYRIC PHYSICAL DESIGN FRAMEWORK

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DC CIRCUIT ANALYSIS OF

INTEGRATED CIRCUITS FOR THE

LYRIC PHYSICAL DESIGN

FRAMEWORK

Submitted by Dennis Weston

for the degree of

BSc (Hons) Computer Science

2006

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DC CIRCUIT ANALYSIS OF INTEGRATED CIRCUITS FOR THE LYRIC PHYSICAL DESIGN FRAMEWORK

Submitted by Dennis Weston

COPYRIGHT

Attention is drawn to the fact that copyright of this dissertation rests with its author. The Intellectual Property Rights of the products produced as part of the project belong to the University of Bath

(see http://www.bath.ac.uk/ordinances/#intelprop).

This copy of the dissertation has been supplied on condition that anyone who consults it is understood to recognise that its copyright rests with its author and that no quotation from the dissertation and no information derived from it may be published without the prior written consent of the author.

Declaration

This dissertation is submitted to the University of Bath in accordance with the requirements of the degree of Bachelor of Science in the Department of Computer Science. No portion of the work in this dissertation has been submitted in sup-port of an application for any other degree or qualification of this or any other university or institution of learning. Except where specifically acknowledged, it is the work of the author.

Signed...(Dennis Weston)

This dissertation may be made available for consultation within the University Library and may be photocopied or lent to other libraries for the purposes of consultation.

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Abstract

In today’s world, integrated circuits, or microchips, are all around us and affect almost everything we do. They are found in all our electrical products from ev-eryday systems like our computers and our washing machines to the important anti-lock brakes in our cars. Engineers who design these microchips need to make sure they are reliable, especially in safety critical systems such as the flight sys-tems of aeroplanes, before they are manufactured. Circuit analysis of microchip designs can highlight areas which may be unreliable due to the problems of IR drop and electromigration, which can then be corrected by the circuit designers. This project concentrates on designing and implementing a DC circuit analysis system to be used with a specific microchip design tool - the Lyric Physical De-sign Framework - to enable users to provide reliable chip deDe-signs before the cost of manufacture and testing is incurred.

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Acknowledgements

Dr Marina De Vos

For being my project supervisor and providing advice and guidance

Dr Peter Shepherd

For proof reading and providing guidance from an electrical engineering stand-point

Dr Alwyn Barry

For support and advice through some difficult times

The staff at Pulsic Limited, especially Jeremy Birch

For giving me their time and resources to help me complete this project

My family

For their ongoing love and support

David Taylor and James Steward

For always being available to chat and trying to keep my spirits high when I was feeling low

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3 Requirements Analysis and Specification 18 3.1 Requirements Analysis . . . 18 3.1.1 Type of Circuit . . . 18 3.1.2 Inputs . . . 19 3.1.3 Outputs . . . 20 3.1.4 Speed . . . 20 3.1.5 Accuracy . . . 21 3.1.6 Reliability . . . 22 3.1.7 Platform Versatility . . . 22 3.1.8 Security . . . 22 3.1.9 User Interface . . . 22 3.1.10 Heat Map . . . 23 3.2 Requirements Specification . . . 23

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3.2.1 Functional Requirements . . . 23 3.2.2 Non-functional Requirements . . . 24 3.3 Constraints . . . 24 3.3.1 Hardware Constraints . . . 24 3.3.2 Software Constraints . . . 24 3.3.3 Time Constraints . . . 24 3.4 Summary . . . 24

4 Tools and Technologies 25 4.1 Programming Languages . . . 25 4.1.1 C . . . 25 4.1.2 C++ . . . 27 4.1.3 Java . . . 28 4.1.4 Python . . . 29 4.1.5 Conclusion . . . 29

4.2 Integrated Development Environments (IDEs) . . . 30

4.3 Compilers . . . 30

4.4 Debuggers . . . 31

4.5 Revision Control Systems . . . 31

4.6 Backing Up Files . . . 31

4.7 Testing Technologies . . . 32

4.8 Summary . . . 32

5 High Level Design 33 5.1 System Structure . . . 33

5.2 Initial Circuit Analysis Algorithm . . . 34

5.3 Matrix Inversion Algorithms . . . 36

5.4 Iterative Circuit Analysis Algorithm . . . 37

5.5 Units To Be Used . . . 39

5.6 Data Structures . . . 40

5.7 GUI . . . 41

5.8 Summary . . . 42

6 Low Level Design and Implementation 43 6.1 Code Files . . . 43

6.2 Types . . . 44

6.3 Data Structures . . . 45

6.3.1 Matrices . . . 45

6.3.2 Circuit Elements . . . 47

6.4 Filling the Data Structures . . . 48

6.5 Modified Nodal Analysis Algorithm . . . 49

6.6 LU Decomposition Algorithm . . . 51

6.7 Iterative Circuit Analysis Algorithm . . . 52

6.8 Current Calculation . . . 54

6.9 GUI implementation . . . 54

6.10 Intermediate Testing Results . . . 56

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7 System Testing 57

7.1 Test Strategy . . . 57

7.2 System Accuracy . . . 58

7.3 Speed of the Iterative Algorithm . . . 59

7.4 Multi-platform Ability . . . 60 7.5 Reliability . . . 61 7.6 Usability Testing . . . 62 7.7 Summary . . . 62 8 Conclusion 63 8.1 Meeting Requirements . . . 63 8.2 Positive Aspects . . . 64

8.3 Things That Could Be Improved . . . 64

8.4 Future Work . . . 65

8.4.1 Full Chip Analysis . . . 65

8.4.2 Accommodation of Active Circuit Elements . . . 65

8.4.3 AC Circuit Analysis . . . 66

8.4.4 Heat Maps . . . 66

8.4.5 Beyond Circuit Analysis . . . 67

Bibliography 68 A Example ring and mesh from an IC design in Lyric 72 B Screenshots 73 C Test Plan 76 D Circuit Designs for Testing Purposes 78 D.1 Test Design 1 . . . 78

D.2 Test Design 2 . . . 79

E Test Results 80 E.1 System v PSpice using Test Design 1 . . . 80

E.2 System v PSpice using Test Design 2 . . . 80

E.3 Multiple Platform Testing using Test Design 1 . . . 81

E.4 Multiple Platform Testing using Test Design 2 . . . 81

F Output Files from System Testing 82 F.1 Windows XP Pro using Test Design 1 . . . 82

F.2 Windows XP Pro using Test Design 2 . . . 83

F.3 Solaris 8 using Test Design 1 . . . 83

F.4 Solaris 8 using Test Design 2 . . . 84

F.5 SuSE Linux 9.0 using Test Design 1 . . . 85

F.6 SuSE Linux 9.0 using Test Design 2 . . . 86

F.7 Diff of the Output Files of MNA and Iterative Algorithms . . . . 86

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G.1 input.h . . . 90 G.2 input.c . . . 91 G.3 mna.h . . . 109 G.4 mna.c . . . 109 G.5 iterate.h . . . 116 G.6 iterate.c . . . 116 G.7 current.h . . . 123 G.8 current.c . . . 123 G.9 output.h . . . 124 G.10 output.c . . . 124 G.11 utilities.h . . . 126 G.12 utilities.c . . . 127 G.13 nodalAnalysis.h . . . 130 G.14 nodalAnalysis.c . . . 131 G.15 mna interface.h . . . 134 G.16 mna interface.c . . . 135

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Chapter 1 Introduction

1.1 Integrated Circuits

An integrated circuit is a thin chip consisting of at least two connected electronic components, such as resistors, capacitors and, most commonly, transistors. Typ-ical integrated circuits these days are smaller than a squared centimetre in size and can contain millions of interconnected devices.

In today’s world integrated circuits (IC’s) or ’chips’ are all around us and affect almost everything we do. We find them in our computers, our washing machines, our mobile phones - in all electrical equipment. The engineers who design such chips want to ensure that they will be reliable, especially when they are involved in such critical processes such as the flying of an aeroplane or the operation of ABS brakes in a car. A chip failure in one of these applications could cause fatalities and expensive lawsuits plus the cost of recalling/repairing the affected chips.

In order to avoid failures, it used to be the case that chips were produced and tested to verify their reliability before going into full production, however this is an expensive and time consuming solution. Therefore chip designers prefer a software tool which can check the reliability of a chip design before it even gets put into production.

1.2 Electronic Design Automation

Electronic Design Automation (EDA) is a category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to

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in-tegrated circuits [38]. This basically means using computer programs to design, lay out, verify and simulate the performance of electronic circuits on chips and PCBs [9]. Due to the continuous scaling of semiconductor technology as governed by Moore’s Law, EDA tools have become increasingly important in the design of microchips; without EDA tools there would be nowhere near the number of electronic devices on the market as there are today.

1.3 Lyric Physical Design Framework

The Lyric Physical Design Framework, from here on shortened to Lyric, is an EDA tool produced by a company called Pulsic Limited and is the software which this project seeks to improve. Lyric is defined as:

”a high performance auto-interactive IC physical design solution for analog, custom, digital, mixed-signal, embedded DRAM/SRAM and system-on-chip (SoC) design - incorporating solutions for ECO place-ment, routing, timing closure, signal integrity and power routing” [17]

Lyric is a complicated tool, but in simple terms it allows chip designers to lay-out the electrical components required for a particular chip and connect all the components together with interconnects in a process called ’routing’ in order to produce a complete chip design.

To ensure Lyric produces reliable chip designs, it needs to incorporate some software tools that will analyse the design, looking for the issues that can cause chip failure. The results of the analysis should then be reported to the design engineers who can make the necessary corrections. This encapsulates the focus of this project.

1.4 Scope

The domain of this project is a large one as the reliability of a microchip can be influenced by many factors including the correctness of the logic of the chip and errors in the chip introduced during the manufacturing process. However, in order to limit the scope to a manageable level, this project will only be concerned with the important errors which are caused by an excess of current (electromigration) or a reduction of voltage (IR drop) across the circuitry. These errors will be described in more detail in Chapter 2, as will the process of circuit analysis which is a technique to find these errors and the basis of the final system.

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This still leaves a large domain however, for instance there are two types of circuit to think about, alternating current (AC) and direct current (DC). The circuit analysis for DC is done in the time domain while AC analysis is done in the frequency domain. For the purposes of limiting the broadness of the project and to ensure the goal are achievable, the project will only be concerned with DC circuits.

1.5 Aims

The aim of this project is to design a library of functions that will analyse the circuitry of an integrated circuit design to discover any issues that may cause the chip to become unreliable. This library should be able to be integrated into the Lyric Physical Design Framework software as an analysis tool and be able to show graphically the results of its analysis in the Lyric graphical interface. Another major aim, garnered from preliminary discussions with Pulsic Limited, is to ensure the tools provides the ability to quickly re-analyse a chip design after it has initially been analysed and the design edited. This is important as design engineers quickly want to see the effects of any alterations they make to a design as Lyric is a real-time interactive tool.

It is aimed that the analysis tool will produce accurate results and produce said results in a timely fashion comparable to any similar tools on the market. It is also intended that the tool be easy to use for a professional IC design engineer and that the results produced be displayed in a clear and obvious manner.

1.6 Document Structure

The next chapter is the literature review which outlines the issues that can cause unreliability in microchip designs and then goes on to investigate the methods of analysing electrical circuits, any current technology that provides similar func-tionality and existing algorithms which may be useful in the designing of the new tool.

Following on from the literature review is the requirements chapter which studies the task at hand in detail and outlines the exact aims of the project. Further on in the document comes the high-level design chapter and then the chapter detailing the detailed design and implementation of the system.

Chapter 6 looks at the testing of the produced system to assertain how well the finished product meets up with the requirements. The document closes with an

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evaluation of the project as a whole and provides recommendations for future work.

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Chapter 2 Literature Review

2.1 Chip Reliability

As outlined in the scope of the project in Section 1.4 on page 2, this project will be concerned with the important reliability issues caused by IR (voltage) drop and electromigration. Here these issues will be described in detail, looking firstly at IR drop.

The voltage supplied to a chip needs to be carried around the chip effectively in order to provide the power for the electronic components to function. IR drop is due to the resistance of the metal lines of the power network [24] resulting in lower voltages reaching parts of the chip than intended. If there is an excessive drop in the value of the voltage at some node on the chip compared to that which was supplied then there is a problem in the design of the chip as the power is being wasted. With the size of chips getting smaller and the amount of voltage being supplied being lowered proportionally, even a small drop in voltage across a chip can be significant [25]. Drop in voltage can lead to delays in the circuit causing slower performance and also cause logic failures and the inability of some components to function properly since they aren’t receiving enough power. Traditional methods for detecting this voltage drop cannot handle today’s large designs [43] and so are useless for ensuring designs are reliable. An alternative solution is to use electron beam and focused-ion beam studies [43] but the costs involved in these processes can be debilitating in today’s market environment. Therefore an effective software tool which can detect voltage drop during the design phase is invaluable.

Second, is the problem of electromigration in the interconnects (microscopic alu-minium wires) that join up the electrical components on a chip. Electromigration research was pioneered by James R Black. He defined the phenomenon as the

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Figure 2.1: a) A void forming. b) hillocking - short circuits forming [22] transport of mass in metals when the metals are stressed at high current densities [1], where current density is the ratio of current to the cross-sectional area of a conductor. In integrated circuits where the interconnects are now usually less than 130 nanometres in width and carry a relatively high current, the current density is high. Inside the interconnects, atoms of the metal are being bombarded as an ’electron wind’ (current - a flow of electons) [1] tries to rush through it. This results in collisions in which electrons pass on their momentum to the atoms and pushes them out of position. If this happens enough over a period of time, a sufficient amount of atoms will be moved far enough to cause the wire to physi-cally snap, creating what is known as a void [37] and breaking the circuit. (See Figure 2.1. a )

Another outcome of electromigration is that atoms of a connecting wire could be forced into piling up and drifting outward from the metal and possibly join up with a nearby interconnect. This is known as hillock failure or whisker failure (short circuit) [37] and is likely to cause the chip to malfunction. (See Figure 2.1. b )

In order for the two outlined possible causes for chip failure to be avoided, the chip designer needs to know the voltage at every node in the circuit and also the current that flows through each of the interconnecting wires. Knowledge of the voltage across the circuit will allow the designer to see where power is being leaked and so amend the chip design accordingly. Knowledge of the currents at all points across the circuit will show where the current is too high and enable the designer to fatten the wires to reduce the current density and so reduce the risk of electromigration.

The solution to avoiding these problems is to perform circuit analysis on the electrical circuits in a chip design in order to spot where such problems might occur and alter the design accordingly.

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2.2 Circuit Analysis

Circuit analysis is the study of electrical circuits in order to predict the electrical behaviour of physical circuits [7]. Before explaining circuit analysis, here are a few useful definitions: a node is a point in a circuit where three or more wires meet [20], a branch is any path in the circuit that has a node at each end and contains at least one voltage source or resistor but contains no other nodes [20], a loop is where nodes and branches form a ring in a circuit.

There are many different forms of circuit analysis, but as detailed in the project proposal, this project has limited its scope to deal with dc circuits only, so only dc circuit analysis will be described in this report. The circuits are assumed to comprise of one or more voltage sources, zero or more current sources and one or more resistors. The resistors are assumed to be the branches (wires) of the circuits themselves.

In order to conduct circuit analysis on an electrical circuit, there are some basic electrical laws which need to be used. The most fundamental of these is Ohm’s law.

Ohm’s law states that the voltage across a resistance is directly proportional to the current flowing through it. The resistance, measured in ohms, is the con-stant of proportionality between the voltage and current [13]. The mathematical relationship of Ohm’s law is illustrated by Equation 2.1.

V (t) = R × I(t), whereR ≥ 0 (2.1)

which is usually simplified to Equation 2.2.

V = I × R (2.2)

Ohm’s law provides the tools for analyzing simple circuits, but for more compli-cated circuits, such as those you would find in a microchip design, there are two further fundamentals called Kirchhoff’s laws. The first law is Kirchhoff’s current law (KCL), which states that the algebraic sum of the currents entering any node is zero [13]. For example, applying Kirchhoff’s law to the node in Figure 2.2 yields Equation 2.3:

i1+ i4− i2− i3 = 0 (2.3)

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Figure 2.2: Four branches connected to a node

sum of the voltages around any loop is zero [13]. This means that the sum of the voltage drops through the resistors equals the sum of the voltage rises through the voltage sources [21].

Kirchhoff’s laws in conjunction with Ohm’s law can be applied to a complex electrical circuit with multiple loops and nodes in order to determine the voltages and currents at all nodes and branches of the circuit. There are two predominant methods of doing this - nodal analysis and mesh (or loop) analysis.

In nodal analysis, the variables in the circuit are selected to be the node voltages. One node is selected as the reference node and all other node voltages are defined with respect to that node [13]. This node is called the ground node and is assigned a voltage of zero [19].

The process then continues by iterating through the nodes in the circuit and applying Kirchhoff’s current law to each of them. The result is a system of m linear equations in the m unknown voltages (where m is one less than the number of nodes). The equations are of the form:

where G11, G12, . . . , Gmm and I1, I2, . . . , Im are constants [19]. The equations

can be considered a matrix and then solved with Gaussian elimination or some other method giving the voltages for all the nodes. With the node voltages known, the currents along each branch can easily be determined using Ohm’s law. In mesh analysis, the unknown parameters are the current values and Kirchhoff’s voltage law is used to determine them [13]. The method starts by identifying all the loops in the circuit (see Figure 2.3 for a basic diagram).

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producing a system of equations of the form:

where R11, R12, . . . , Rmm and V1, V2, . . . , Vm are constants [18]. As with

nodal analysis, these equations can then be solved as a matrix and the voltage values determined using Ohm’s law.

The choice of which method to use is often dependent upon the circuit to be analysed. If the circuit had fewer nodes than loops, then nodal analysis would be preferable as it produces fewer equations to solve. For the same reason, mesh analysis would be preferable if there are fewer loops than nodes. One other consideration to make is that mesh analysis can only be applied to circuits which are planar, i.e circuits which can be drawn in two dimensions [34]. What this means is that wires in a circuit must not ”jump over” one another in order to apply mesh analysis. For this reason nodal analysis is most commonly used in circuit analysis software, since it is always guaranteed to work.

2.3 Circuit Analysis in Lyric

Currently, Lyric does not include a mechanism with which to analyse circuits in microchip designs which contain loops. Since the circuits in chip designs are usually very complicated with lots of loops, this is quite a problem. At the moment, Lyric only has a very basic tool with which to analyse only parts of the circuits where no loops occur.

According to Jeremy Birch, Chief Technology Officer at Pulsic Limited, Lyric currently employs a basic dendritic method for circuit analysis. It is called den-dritic as it follows a simple tree/branching strategy and takes as input nodes at

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Figure 2.4: Simple dendritic analysis strategy for determining branch currents which the current is known and then it is easy to work out the currents that flow through the branches. For example, in Figure 2.4 it is known that 5mA are enter-ing the branch at X and that devices at Y and Z draw 3mA and 2mA respectively, then the value of current which flow through the branches are obvious.

As this method only works for the most basic of examples, Lyric is in need of a proper circuit analysis tool, which is the purpose of this project. A key feature for any such tool is that it needs to be interactive - that is, it should quickly show how small changes to the circuit effect how the circuit behaves. This is important so chip designers can create reliable designs.

Computer-based circuit analysis tools have been developed since the 1960’s. In order to understand how circuit analysis tools work and the methods and tech-nologies available, a few circuit analysis tools are explored here.

2.4 Existing Circuit Analysis Systems

2.4.1 ECAP II

ECAP II, Electronic Circuit Analysis Program, is a circuit analysis program that was first devised in 1971. It has no graphical user interface and instead features an input language for users to enter the details of a circuit design, with FORTRAN sub-routines [2].

The method by which the program carries out circuit analysis is not by us-ing nodal analysis or mesh analysis but rather by a process called the mixed method. This method utilises the idea that Ohm’s law can be expressed in a matrix form involving the admittance matrix for certain branches of the circuit and the impedance matrix for the rest of the branches [3]. Impedance is an ac circuit term which is analogous to resistance in a dc circuit and admittance is analogous to conductance in dc circuits which is the reciprocal of resistance [13].

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The admittance branches are then analysed with a method called the cutset method and the impedance branches by the mesh method. The two sets of linear equations are then combined into one matrix and solved. The method of solution, rather than using the straight-forward Gaussian elimination, uses implicit integration based on the variable order approach of Gear [10] as modified by Brayton et al [4]. This method approximates a solution and then iterates -converging towards the actual solution. This only takes one or two iterations for a dc problem [2] and is faster than the Gaussian approach.

An advantage of ECAP is that it contains a modify feature [3] which is based on Kron’s tensorial method as explained later in this paper. The modify feature allows the matrix of solutions for a circuit to be updated in relation to changes in some branch resistances with only trivial computation compared to re-calculating the entire solution from scratch. This is a feature that is needed for a circuit analysis tool for Lyric since it needs to be an interactive design tool and so this method could be adopted.

A possible disadvantage of this program is the complex method by which the systems of equations are constructed and solved. It would be much simpler to construct the matrices using nodal analysis and solve them using Gaussian elim-ination. It’s true that ECAP’s method is faster but is this increase in complexity worth the time gain? Also, with the speed of modern computers the increase, in speed may be minimal.

2.4.2 SPICE

SPICE, Simulation Program with Integrated Circuit Emphasis, is a circuit simu-lation program developed in the 1970’s at the University of California, Berkeley. It is a derivative of another circuit analysis program, CANCER, that was also developed at Berkeley [23].

SPICE is the most widely used circuit analysis program in the market place and has many derivatives of its own such as SPICE2, SPICE3 and PSPICE which is the pc version of the software owned by Cadence Design Systems.

Like ECAP, SPICE was designed to have no user interface as standard and was used via an input language. Programs were written in the input language, saved and then compiled into an executable [8]. SPICE took as input a netlist file which describes the circuit, which was then fed to the executable to perform the analysis. More recent incarnations of SPICE have a full graphical user interface and circuit designs can be entered into the system by placing circuit components onto a canvas to form a schematic for the circuit.

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of SPICE is nodal analysis as seen in steps 3 and 4. For linear dc circuits, these are the only stages that are necessary. The inner loop, steps 2 - 6, iterates to find the solution for non-linear dc circuits, while the outer loop, 7 - 9, extends the process for ac analysis.

As this project’s scope is only linear dc circuits, steps 3 and 4 are the impor-tant ones. As mentioned above, SPICE’s analysis mechanism of choice is nodal analysis. SPICE creates the matrices for the systems of equations in the form

with the G matrix being a matrix of the conductances (1/resistance), the I vector being a vector of branch currents and the V vector being the vector of the node voltages. The V vector is where the solutions will appear at the end of the analysis.

SPICE uses a shortcut called matrix construction by inspection to create the ma-trices rather than creating a system of nodal equations using Kirchhoff’s current law. This inspection method allows SPICE to create the system matrices as each element is read in from the input file at the start of execution.

”Matrix construction by inspection builds the system matrices and identifies the location of each element in the matrices as soon as the nodes connected to the element are defined [15]”

For solving the matrices, SPICE uses a form of Gaussian elimination called LU (or triangular) decomposition. This method of solution is faster than normal

Gaussian elimination. Standard Gaussian has a complexity of O(n3_{/3) whereas}

LU decomposition has a complexity of O(n3_{/3 -n/3) where n is the number of}

rows in the matrices [14].

Later incarnations of SPICE replaced nodal analysis with an improved system called Modified Nodal Analysis (MNA). MNA was designed to rectify the short-comings of standard nodal analysis. These drawbacks include the fact that nodal analysis treats voltage sources inefficiently and is incapable of including current-dependent elements. Another issue is the fact that the nodal method does not produce the currents through the independent voltage sources as part of the out-put [12]. These have to be calculated later using Ohm’s law at each of the circuit nodes and so adds to the computation required.

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MNA resolved all of the problems of the nodal approach while preserving its ad-vantages [12]. MNA produces the currents through the voltage sources as well as the node voltages as part of its output while also reducing the complexity of computation. While the order of the matrix equation is increased (the algorithms only overhead), the equations are generally highly sparse and can take advantage of efficient routines to solve sparse matrices. Also MNA indicates the most ef-ficient ordering for the LU decomposition process, speeding up the process of finding the solutions [32].

Results from [12] shows MNA outperforms another common approach to circuit analysis - the tableau method. The advantage of SPICE’s mechanism is that it uses algorithms which are reliable and easy to use. The algorithms have been around for decades and are proven to be useful and there is also a lot of supporting literature which would be useful in implementing a SPICE-like system in Lyric. The disadvantages include the fact that an O(n3) algorithm on matrices with thousands of lines may take a fair amount of time to compute. Also, unlike ECAP, SPICE does not allow quick re-analysis when there have been small changes to the circuitry, the analysis has to be restarted from the beginning which takes time. Quick re-analysis is fundamental to any analysis tool to work well with Lyric.

It may be useful to use some of SPICE’s methodology to create a circuit analysis tool for Lyric but it is not the whole answer.

2.5 Other algorithms

2.5.1 Kron’s Method of Tearing

This method invented by [16] is supposed to make it possible to solve very large physical problems in easy stages. The method involves tearing a large system of equations up into a large number of small subdivisions, solving each subdivision separately and then interconnecting the partial solutions by a set of transforma-tions to obtain the solution of the original system [16]. It is important that the tearing is carried out such that each component part produced is independent of every other part so that each can be solved independently before amalgamating them to form the whole solution.

The main advantage of this tearing (or tensorial) technique is that the amount of computation required to solve the system of equations is reduced by a significant amount. For example, taking the system I = YE, where I, Y and E are matrices, and dividing it into n parts, calculating the inverse E = ZI is reduced by a factor

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of 2/n2 _{[16]. If n = 100, the calculations are reduced to a fraction of about}

1/5000.

Other advantages include the fact that if several of the subdivisions are identical, the reduction in computation increases dramatically. Also, if a system is already solved and is then altered in any manner, the solution of the altered system need not be started from scratch. Only the solutions of the altered portions are changed, the rest of the solutions remaining unchanged [16].

In [3], a method is presented by which Kron’s method may be used to study the effects of varying a single resistance in a circuit. This method permits the nodal solution matrix to be updated in accordance with changes in one or more branch resistances. This feature would be very good in a circuit analysis system built for Lyric as it would allow quick recalculation of the circuit properties as the engineers make changes to their designs.

It is also stated in [3], however, that using this technique to compute a sequence of solutions as a given resistance is varied through several different values may introduce round-off errors that accumulate from one step to the next. This would invalidate the results acquired from the analysis.

This implementation of Kron’s tensorial method may provide an ideal solution to quickly calculating the affects of small changes made to a circuit by chip designers. It remains to be seen however if the round-off errors can be avoided.

2.5.2 Cholesky Factorisation

Cholesky factorisation is a technique for solving sparse matrices. The method states that if matrix A is positive definite, then there exists a unique lower tri-angular matrix G with positive diagonal entries such that A = GGT _[11].

This method does not require pivoting as in the LU decomposition method for solving matrices and hence its performance is twice as fast [31]. The technique is also fairly easy to implement, however it can only be used on matrices that are symmetric and positive definite.

2.5.3 Hierarchical Analysis Algorithm

This algorithm is based on the well-known strategy of divide and conquer and compromises the following: (1)The power grid is divided up into local and global grids, (2) macromodels are generated for the local grids, (3) the admittance (1/resistance) matrix is sparsified, (4) the global grid is modelled using the local

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grids and finally, (5) simulating the local grids where desired [44].

As with other divide and conquer algorithms, this method benefits from solving many simple problems rather than one large problem. Further improvements in computation are gained by the sparsification of the matrices so that they may be solved quickly using efficient sparse matrix solving algorithms. [44] shows that the hierarchical analysis method is significantly faster than conventional non-hierarchical methods.

The disadvantage of this method is that implementation may be difficult due to the complex nature of the algorithm. Also, the algorithm relies on a hierarchical structure in the design of the circuit which often may not be the case.

2.5.4 Random Walk Algorithm

This is a new method for analysing circuits, more specifically power grids, based on the relationship between random walks and electrical networks [27]. The method is inspired by the work of Doyle and Snell [28] which interprets the relationship between resistive networks and probabilities.

[27] shows that using Kirchhoff’s laws, the voltage at any node in a circuit is a linear function of the voltages at its neighbours. This is analogous to a random walk problem so that for any power grid problem, a mathematically equivalent random walk problem can be constructed i.e characterised by the same set of equations [27].

By finding an approximate solution to the random walk problem, an approximate solution to the circuit problem is also found. The solution is found by conducting a certain number of experiments on the random walk and averaging out the voltages returned to give the approximated solution.

”If this amount is averaged over a sufficiently large number of walks by playing the ’game’ a sufficiently large number of times, by the law of large numbers [42], an acceptably accurate solution can be obtained [27]”

There is an accuracy-runtime trade off with this algorithm that means the more accurate the solution you want, the longer it will take to compute. The number of walks carried out, and so the accuracy of the solution, is governed by a user specified variable. This algorithm should be capable of an accuracy of above 99% however.

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The algorithm has linear complexity [27] and so when testing against other meth-ods is found to be much faster. Another plus point is that the algorithm localises computation; it can calculate a single node voltage without having to solve the whole circuit which is a desirable feature in an interactive design and analysis tool.

A disadvantage of this method is that the algorithm seems to be fairly complex and so implementation might be difficult. Also the algorithm only produces node voltages so the branch currents would have to be worked out afterwards using Ohm’s law, which adds to the computation time. The other disadvantage is that the results are close approximations rather than actual voltages and so there is a small margin of error introduced.

2.5.5 Hierarchical Random Walk Algorithms

The hierarchical random walk algorithms combine the divide and conquer idea of the hierarchical analysis algorithm with the random walk method [28]. This method proves to work roughly three to four times faster than the standard random walk method while also being more robust.

While being very fast this algorithm does have the drawback of being more com-plicated to implement than the two algorithms it is based on. It also has the same problem that the branch currents are not calculated as part of the analysis and so will have to be done separately at the expense of extra computation.

2.6 Conclusions

The method as employed by SPICE is the most easy to understand and implement while being the best supported and probably the most reliable. However, as it is not a suitable solution as an analysis tool in an interactive design environment, it cannot be the whole solution for this project.

Using the SPICE method as first pass analysis would provide a good base for further analysis. Then Kron’s tensorial method or a random walk algorithm or some other similar algorithm could be useful for providing quick re-analysis when small changes are made to the circuit.

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Chapter 3 Requirements Analysis and

Specification

3.1 Requirements Analysis

This chapter aims to determine all the goals of the system to be created and set them out as a specification for the design stage. The best way to elicit the requirements for a new software system is to enlist the help of the experts in the area. Since this circuit analysis system is to be incorporated into the Lyric Physical Design Framework, it makes sense to talk to the engineers at Pulsic Limited who make the software and therefore know what they want from a new tool.

Jeremy Birch is a co-founder of Pulsic and currently works as the Chief Tech-nology Officer. He is widely recognised within the company to be the foremost expert on the software and has been the principal contact within the company for this project. The documentation of the requirements process here comes largely from discussions with Jeremy Birch, with some input from a few other employees.

3.1.1 Type of Circuit

As mentioned in Section 1.4 on page 2, this project is focussing just on the DC aspect of IC circuits and ignoring the AC aspect in order to help set a manageable task. This still leaves a very large scope for the project, so it needs further refining. Electrical circuits can contain active devices and passive devices. Active devices are either sources of energy, driving electrical current around the circuit and hence delivering continuous energy to it [33], or else they have the ability to control the

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flow of electricity. The most common active device is the transistor. Passive devices are those which consume energy rather than produce it, like resistors, inductors and capacitors [33].

Since active devices control the flow of electricity, they are much harder to model than the passive devices which only consume it. To make this project of achievable size, the circuit analysis tool that is to be produced will operate on circuits consisting of passive elements only.

Further more, since modern integrated circuits can contain more than ten mil-lion components with interconnects in between, this project will concentrate on analysing specific sections of the chip. These sections are known as ’ring and mesh’. They consist of a ’ring’, which is a relatively large power track, and lo-cated within it is a ’mesh’, which is a grid of thin wires, the edges of which are connected to the ring. The mesh carries power from the ring to the components situated beneath.

Ring and mesh circuits are suitable for this project since they can be easily modelled. The wires are modelled as resistors, the connections between the mesh and the power ring can be modelled as independent voltage sources and the drain of current from the components below the mesh can be modelled as independent current sources.

3.1.2 Inputs

To perform circuit analysis, the system needs to know the architecture of the circuit - that is, how the nodes of the circuit are connected together by the branches (wires), and also where any independent voltage sources and current sources are connected.

In a stand-alone library with no graphical user interface, this information can be fed into the system manually. The user could simply enumerate the nodes, branches, voltage sources and current sources and type the details into a command line interface. This is similar to how OrCAD SPICE works, albeit without the graphical user interface. In SPICE, users drop onto a schematic the components to create the circuit they desire before running any analysis. Entering the circuit information via a command line interface might be useful for implementing small circuits for test purposes, but it would be very tedious.

If the circuit analysis system is to be integrated into Lyric then it is likely that the circuit information will have to be inputted in the same way that the information is entered into Lyric which is via a netlist file. This is a special file format that contains all the information for the circuitry in a chip design which is read and stored appropriately.

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3.1.3 Outputs

As stated in Section 2.1 on page 5, the system created by this project is intended to help chip designers reduce the possibility of electromigration and IR drop occurring.

Since electromigration is caused by an excess in the flow of current through a wire, the system needs to be able to calculate and output the value of the current flowing through every branch between the nodes of the circuit. In order to make it easy for a chip designer using the system to see where there is an overflow of current, it would be useful for the system to highlight where there is a current that exceeds acceptable limits. It would be simple then for the user to see the places where the wire should be fattened to reduce the stress.

A possible addition to this functionality which would be a bonus to the user would be for the system to highlight areas where the current flow is significantly under the maximum capacity of a wire. With this information, the user could make the wire thinner and thus possibly make the overall design smaller, resulting in a smaller physical chip size.

To recap on Section 2.1, IR drop is the phenomenon whereby voltage drops ex-cessively across a circuit, possibly resulting in not enough power reaching certain areas of the chip. Therefore, the system needs to output the voltage at every node across the circuit. To make it easier for the user to see where problems may occur, it would be of benefit if the system could highlight nodes where the voltage is below some predetermined threshold level.

An enhancement to this functionality would be for the system to indicate where a node is receiving a large excess in voltage. This might allow the chip designer to reduce the power input into the chip.

3.1.4 Speed

The initial attempt at circuit analysis, when the system first calculates the values for voltage and current across the specified circuit, does not have to be partic-ularly fast. When Lyric’s router tool runs and joins up all the components in a chip design with wire tracks, it can take an hour or more, depending on the size of the design. So, relative to this, conducting circuit analysis will be comparatively fast anyway so there is no real need to strive for speed for the first iteration. The focus at this point is simply accuracy and reliability.

The results of the first circuit analysis will often show areas of the circuit where currents and voltage fall outside the specified parameters. In a mesh with ten

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thousand nodes, and thus more than ten thousand branches, there maybe hun-dreds of such errors that need correcting.

Fixing the errors highlighted by the circuit analysis is done by either fattening the wires or thinning them. For instance, if there is too much current flowing through a wire then the wire needs fattening to safely accommodate the current flowing through it.

However, a single fattening of the wire will not normally fix the problem. By fattening the wire, the resistance of the wire is reduced causing more current to flow through it, which could mean the fattening has little effect. The solution then is to fatten or thin the wire iteratively and re-analyse to see the effects of the action and find the optimum wire width. The wire needs to be fattened enough to safely cope with the current flowing through it but not so much that the amount of current increases enough to negate the fattening. The thinning process is similar to this.

The chip designer may chose to do the fattening/thinning of the wires in the design by hand. More likely though, since there may be hundreds of wires in a design that require the iterative fattening/thinning process, there will be an automated fixing tool that does the job.

Since there will be a lot of iterations of making changes to the design and then re-analysing of the circuit, it is imperative at this point that the circuit analysis is done very quickly. The automated fixing tool has to wait on the results of the analysis before making its next change and so it cannot have to wait long or the whole process would take an impractical amount of time.

The focus therefore during this area of the systems usage is speed, but still with as high accuracy as possible, although some slight trade-off may be acceptable.

3.1.5 Accuracy

Since the circuit analysis is being performed on integrated circuits, the width of the wires is tiny and so the values of the currents and voltages are also very small. The current flowing through any wire in the circuit may range from one amp down to a few nano amps while it also must be possible to detect a drop in voltage of one ten-thousandth of a volt between adjacent nodes. The system will have to be able to manipulate these small numbers accurately and ensure the possibility of round-off errors is avoided

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3.1.6 Reliability

The system to be produced by this project is just simply for academic purposes; Pulsic wish to integrate it into their Lyric software. This means that the system will have to live up to the reliability expectations of the business world. Pulsic’s customers will expect a high level of reliability since they will have spend a lot of money on the Lyric tool.

This implies that the testing performed in this project should be as rigorous as possible to catch any bugs and errors in the system.

3.1.7 Platform Versatility

Pulsic provides versions of its software to run on a wide variety of platforms to suit all customer needs. The range of platforms includes Linux, Solaris, HP-UX and Windows. Further more, Pulsic support different varieties of each of those platforms. For Linux for instance, Lyric is available to work with SuSE 9.0, SuSE 9.1, SuSE 10, RedHat 7.2 and RedHat 8.2.

If this system is to be integrated into Lyric, then it too must be able to run on all of these different platforms. This means taking into account things such as variations in the compiler available etc. Thorough testing should be employed to ensure the system runs correctly on all platforms.

3.1.8 Security

It is important that the software Pulsic release is protected so that other com-panies cannot dissect the code and learn all of the company’s design secrets. Therefore, if this system is to be integrated into the Lyric, it is important that it does not violate any security protocols put in place by Pulsic so that the software remains secure.

3.1.9 User Interface

If the system is to be integrated into the Lyric software, it will have to use Lyric’s graphical user interface rather than having one of its own. This will probably involve adding a menu and some toolbar buttons to the GUI for controlling the circuit analysis tool’s functionality. The circuitry for circuit analysis to be per-formed on will probably be chosen by selecting sections of a chip design displayed

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in the Lyric GUI. The output of the system will also have to be displayed in the Lyric graphical user interface, in some appropriate fashion.

The changes made to the Lyric GUI will have to be made in such a way to keep it consistent, so as not to confuse users. The additions for the new system should be clear and compact to ensure ease of use.

3.1.10 Heat Map

As the number of components on a chip continues to increase along with the den-sity in which they are packed, overheating is becoming a serious factor affecting the performance of integrated circuits.

As part of its functionality, the system could calculate the heat generated by a chip based on the results of circuit analysis. This would require calculations involving thermodynamics and heat conductivity of the various materials from which an integrated circuit is constructed. The results would then be displayed in a ’heat map’ superimposed over the image of the circuit.

However, the complexity of the calculations required for this task to be performed is huge and therefore this requirement is considered to be out of the scope of this project.

3.2 Requirements Specification

3.2.1 Functional Requirements

• Perform circuit analysis on DC ring and mesh circuits containing passive

components

• Take as input the circuit architecture, including the nodes, branches,

volt-age sources and current sources

• Perform an accurate first iteration of circuit analysis • Execute fast further iterations of circuit analysis • Output the voltages at each of the nodes

• Output the currents through each of the branches • Display the results graphically on the Lyric GUI

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3.2.2 Non-functional Requirements

• Output accurate results • Have good reliability

• Uphold Pulsic’s security protocols • Be easy to use

• Be able to run on all the platforms that Pulsic support

3.3 Constraints

3.3.1 Hardware Constraints

The author has been given use of an AMD Athlon PC with 512Mb of RAM by Pulsic. The author also has their own Pentium 4 3.1GHz notebook with 512Mb of RAM and the author also has use of the PCs available on campus at the University of Bath.

3.3.2 Software Constraints

The author has use of the Windows XP operating system on their notebook, the SuSE 9.0 Linux operating system on their Pulsic machine and the UNIX operating system on the University of Bath computers. Servers at both Pulsic and the university also provide compilers for most mainstream languages that the author may wish to use.

3.3.3 Time Constraints

The final deadline for the project is Monday 8th May.

3.4 Summary

This ends the Requirements Analysis and Specification chapter. The next chapter investigates the various tools available for implementing the system and chooses the best ones for the task.

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Chapter 4 Tools and Technologies

4.1 Programming Languages

There are various languages available that could be used to implement the current analysis system. Here is a discussion of some of those languages, leading to a decision on which should be used.

4.1.1 C

Advantages

C has a simple, small core language with extra functionality being provided by a large range of libraries which include maths and file handling functions [36]. This allows programmers new to the language to quickly become proficient in the basics, while the more complicated routines are readily available when needed. The language the supports procedural programming paradigm [36] which lends itself to modular design. While C does not force modular design upon the pro-grammer, good programmers can use the language to create a cohesive modular structure. The modules are usually separate files which can be compiled sepa-rately. This would be useful for this system since it has been designed as a set of modules with specific functionality.

C is extremely flexible and allows the programmer to have low level control over the computer. As such, the programmer has full control of memory allocation and pointers to create program solutions which are tailored to the problem. The low level nature of the language also results in the language being fast in its

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execution. This is a feature which would be welcomed for this system as there are parts of it which need to run as fast as possible.

Through the use of special keywords, C allows the programmer to create new data types to suit the needs of the program solution. This is particularly advantageous for this project as some unique data structures will be needed to store the data for the objects in the system such as nodes, branches etc.

The Lyric Physical Design Framework is programmed largely in C. If this system is also programmed in C, it would be easy to integrate it into Lyric which is an obvious advantage. Furthermore, the author has extensive experience of using C which would mean implementing the system in this language would be easier.

Disadvantages

One disadvantage of C is that memory allocation has to be done explicitly by the programmer. This can lead to errors when memory is not allocated properly. Allocated memory is also not initialised automatically [36] and so this too has to be done by the programmer to avoid getting bizarre values when trying to access data structures. If C is used, these disadvantages mean that the author will have to be particularly vigilant when allocating the memory for the data structures which will doubtlessly be needed.

C is not a strongly typed language. This means that the compiler will often not complain when a variable is declared as one type and then used to store a value of a different type. Therefore, if using this language, the author will have to be careful when writing the program to ensure variables are used as declared to avoid getting any unusual behaviour.

C has some idiosyncracies in its syntax which can catch the programmer out and cause unexpected behaviour in the program. A well known example of this is accidentally using if (x = 0) instead of if (x == 0). The former will set x to be zero rather than testing if x is equal to zero. This will usually cause the program to run differently than expected, but it will not be picked up by the compiler. Other such syntax issues include the ”dangling else” and loops that only iterate over the first line if a block if the curly braces are forgotten. These issues mean the programmer has to be very careful when writing a program to ensure the code will perform exactly as they are expecting.

The disadvantages above can mean debugging C code can be problematic which means the author will need good debugging skills.

C also has no automatic garbage collection which means the programmer has to explicitly free all allocated memory.

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4.1.2 C++

Advantages

Since C++ is derived from C, it inherits many of the advantages of C such as support for procedural programming, the ability to create bespoke data structures and its general flexibility.

C++ supports object-oriented programming [35]. This allows programs to be organised as a collection of classes and objects, which, enthusiasts claim, makes programming large systems easier. If the circuit analysis system had been de-signed with object oriented programming in mind, this would be an advantageous feature. However, the author is more comfortable with the procedural paradigm which is why the system has been designed in a modular fashion instead.

Despite the extra functionality included into the language to support object ori-ented programming, C++ remains a fast language which is an advantage for the iterative circuit analysis tool which relies on speed.

The majority of Pulsic’s source code is written in C, while a good portion is written in C++. This means that if the system was written in C++, it would be easily integrated into the Pulsic software.

The author has little experience with C++, but the fact that it is a derivation of C and that the author has a lot of experience using C, learning C++ should not present too much of a challenge.

Disadvantages

Since C++ is derived from C, it inherits many of the disadvantages of that language too, such as the idiosyncracies of the syntax and the lack of garbage collection.

While the core of the C++ language is small like C, there are many libraries that deal with the additions for objected oriented programming which can make it seem like a large and complicated language [35]. If programmers try to use all of the functionality at their disposal, then it can be a difficult language to master. The additional functionality can also make C++ a slower language than C. Furthermore, while the standard library has been developed by many users over the years to become useful and reliable, many other libraries have not. This can cause problems when trying to develop programs that utilise these libraries. The C++ language contains constructors and destructors that are supposed to

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help with memory allocation. In reality however, they can often hide a lack of deallocation of memory which then leads to memory leakage.

The error messages produced by a C++ compiler are notorious for being ex-tremely complicated and difficult to understand. This will mean choosing C++ to implement this system will require a lot of effort when it comes to debugging the program.

4.1.3 Java

Advantages

Java’s syntax is heavily derived from that of C/C++ [40] and so it should look familiar and be easy to learn for those programmers who have experience with either of those languages. The author has had some experience with Java, which is an advantage should Java be chosen as the language to be used to implement the circuit analysis system.

Java hides the details of the machine from the programmer. For instance, the programmer does not have to worry about pointers or explicit memory alloca-tion. Java has automatic garbage collection [40], so implementing the system in this language would mean the author would not have to worry about explicitly freeing the memory used by any data structures. These features should make implementing the system easier.

Since it is compiled to bytecode which can run on any machine with a Java Virtual Machine (JVM), Java is an extremely portable language [6]. This is an advantage for this project since the circuit analysis system has to be able to run on a variety of different machines and operating systems. Simply by installing a JVM on each of the platforms, the program would be able to run without any changes to it.

Disadvantages

Java is a pure object oriented language [40]. This means the design of the system would have to be changed to be organised in terms of classes and objects rather than the modular design it currently has, if Java is to be used. The author is also more comfortable with the procedural programming style rather than the object oriented approach.

The inclusion of features such as an automatic garbage collector and the fact it is an interpreted language means that Java is generally recognised as being a fairly

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slow language [6]. This is a disadvantage because, as discussed previously, speed is important in certain parts of the system.

As Java hides away the complexities of the underlying machine away from the programmer, the language may be considered to be less flexible than C/C++. There may be occasions when implementing the system where having tight control over the machine may be beneficial, but this is something which Java will not be able to allow.

As a company Pulsic does most of its programming in C or C++. This means that it will be more difficult to integrate a system programmed in Java into Pulsic’s software than if the system were programmed in either C or C++.

4.1.4 Python

Python is an object oriented language that is good for graphical user interface programming. This is because of its Tkinter package which is a thin object oriented layer on top of Tcl/Tk - a graphical user interface toolkit [41]. As such, Python is the language that Pulsic use to implement all their GUIs.

Pulsic also have a customised set of GUI widgets known as pwidgets. pwidgets are created simply by putting a ’wrapper’ around the normal Tcl/Tk widget set to give the widgets a look and feel that make them unique to Pulsic.

Since the circuit analysis system will be integrated into Lyric and will use the same GUI, this project will use Python for any additions that need to be made to the interface. This is the obvious choice so that there wont be any need to integrate a foreign programming language into the GUI software. Furthermore, its imperative that any additions to the GUI retain the same look and feel as the rest of it. Therefore it is necessary that the added widgets are created from the pwidgets widget set, which means using Python.

4.1.5 Conclusion

Having considered the pros and cons of the major languages available for imple-menting the circuit analysis system, the decision has been made to use C. This is because the author has extensive knowledge of the language which should reduce implementation time and also the majority of the Lyric source code is written in C which should mean integrating the two systems should be an easier task. Furthermore, C is a fast language which will help enable the system to meet its performance requirements, and the language supports the procedural

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program-ming paradigm which is the author’s preferred programprogram-ming style.

As for implementing the graphical user interface of the system, the only option really is to use Python since it will enable an easy integration into Lyric and also maintain Lyric’s look and feel.

4.2 Integrated Development Environments (IDEs)

An integrated development environment (IDE) is a piece of software that assists programmers to develop programs and usually consists of a source code editor, a compiler, build automation tools and a debugger [39]. They are generally supposed to make developing software easier.

There are several IDEs available for the C programming language such as Eclipse, C-Free and the CodeForge IDE. However, the author has never used an IDE and feels comfortable programming without the aid of one. Therefore an IDE will not be used when implementing the circuit analysis system.

4.3 Compilers

A compiler is a piece of software that converts the source code of a program written in a programming language into machine code that can be executed by a computer. There are many compilers available for the C programming language, but the author has always used the GNU Compiler Collection (GCC) compiler and feels most comfortable with it.

GCC is produced by the GNU Project and is free software, distributed by the Free Software Foundation (FSF). Since it is open source software, GCC has been de-veloped using the open source model in which users are treated as co-developers. Users are given access to the source code and are encouraged to develop new fea-tures, fix bugs, update documentation and so on. Advocates of the open source development methodology claim that in many ways it is better than the closed source method (commercial development). The open source enthusiast Eric S. Raymond goes so far as to suggest that the open source methodology is able to produce higher quality software than any other methodology or technique [29]. These claims can be partly backed up by studies that have shown that the time taken from bug discovery to bug fix is shorter in open source development. The result for GCC is a highly developed and tested piece of software that should be reliable and efficient. For these reasons and since the GCC compiler is available both on the University of Bath machines and on the computers at Pulsic, GCC

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will be the compiler of choice for this project.

4.4 Debuggers

Debuggers are software tools which help programmers identify the errors in their source code. There are several debuggers available for C, such as the DDD and GDB debuggers available on the Pulsic computers.

Much of the debugging required can be performed manually with the careful insertion of print statements. However, for the difficult to find problems such as errors involved with pointers and memory allocation, the GDB debugger will be utilised.

4.5 Revision Control Systems

Revision control is concerned with keeping track of the development and multi-ple revisions of the same units of information. Revision control systems keep a repository of files which developers ’check out’ in order to work on them before checking them back in and merging the changes made into the previous version. A history of the revisions is kept to ensure that the files can be reverted back to a previous version if necessary. These systems allow a team of people to work on the same files without having to worry about the conflicts between their work or fear of causing damage.

A popular revision control system is the Concurrent Versions System (CVS) which is available on the Pulsic computers. However, since there will be just one de-veloper working on the circuit analysis system, there is no need for a central repository of files for concurrent development and so CVS will not be utilised in the development of the system or its documentation.

4.6 Backing Up Files

Unforeseen technical problems can occur within a computer, such as the hard drive failing or becoming corrupt, that can lead to the loss of files. For this reason important files should not be kept in just one location, they should be ’backed up’. This means copying the files to some other storage device or devices so that if any files are somehow lost, there is always a reserve copy.

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As a precaution in this project, the system’s files will be regularly backed up to the university’s servers, and also to a USB memory stick to allow for file recovery on the move.

4.7 Testing Technologies

Since Modified Nodal Analysis revolves around solving equations involving ma-trices, Maple has been chosen as a platform for testing the circuit analysis system as it is being developed.

Maple is a computer algebra system and as such is excellent at manipulating matrices quickly. It is intended that, during development the system will be tested by giving it some simple inputs and then printing out the matrices that are constructed and the solutions that are calculated. Meanwhile, for the same inputs the matrices are constructed by hand and then the solutions found by using Maple. Comparing the results will show whether the system is working correctly or if some changes are required.

4.8 Summary

In summary, the language to be used for implementing the core system is C, while Python will be used for some of the GUI work. The compiler will be GCC, the debugger will be GDB and Maple will be used for the testing of prototypes. The next chapter will outline the high level design of the system.

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Chapter 5 High Level Design

This chapter outlines the high level design decisions made in order to create a system that satisfies the requirements laid out in the Requirements Analysis and Specification chapter.

5.1 System Structure

The system has been designed in a modular fashion so that the system consists of a collection of units with a distinct functional purpose. It has been designed this way as the problem lends itself more to a procedural approach rather than the object oriented approach which would have led to the system being designed as a collection of classes and objects.

Figure 5.1 displays the overall high level design of the system. It shows that the system is broken down into five modules: the input module, the initial circuit analysis module, the iterative circuit analysis module, the current calculation module and the output module.

Following is a brief description of each of the modules:

• Input - this module is responsible for receiving the input of the system

(circuit layout information) and storing it. This will involve entering the data into the system’s data structures in an organised and efficient manner.

• Initial Circuit Analysis - this module will carry out the first iteration of

circuit analysis on the circuit information held in the system’s data struc-tures. The focus of the circuit analysis at this point is to determine accurate values for the voltage at each of the node in the circuit design. The nodal voltages will then be saved back to the data structures ready for output.

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Figure 5.1: The high level design of the circuit analysis system

• Iterative Circuit Analysis - this module will take the results of the initial

analysis and perform further iterations of circuit analysis. The here is to recalculate the nodal voltages very quickly in response to minor changes made to the circuit so that errors in the design can be fixed in an efficient manner.

• Current Calculator - since the circuit analysis modules only calculate the

nodal voltages, this module calculates the currents through the circuit branches. This will be done by applying Ohm’s law to a pair of nodes and the branch between them. The results will be saved back to the data structures.

• Output - this module is concerned with returning the results of each

iter-ation of the circuit analysis to the user. The most important method of output will be via a graphical user interface, although the results of the circuit analysis will also be printed to a file. This is so users will have a record of the results, but also because it will be useful for system testing.

5.2 Initial Circuit Analysis Algorithm

As stated in Section 3.1.4 on page 20, the requirement of the initial circuit analysis phase is accuracy and reliability with the speed of the algorithm of less impor-tance. With this in mind, the decision of which method to use for this phase of

DC CIRCUIT ANALYSIS OF INTEGRATED CIRCUITS FOR THE LYRIC PHYSICAL DESIGN FRAMEWORK