Common-Source Amplifier

So far, the performance of the model has been confirmed only for digital circuits. Now it is important to move to the analog area as well. Note that we have only considered the large- signal model of the MOSFET. One may suppose that for analog circuits there must be a separate small-signal model defined. However, this is unnecessary and in fact inappropriate simply because the small-signal model is a linear approximation. The linearized small-signal model is utilized to simplify the lengthy manual calculations and is only suitable during the regions where current and voltage can be adequately resembled with a straight line. Hence, the model elaborated in this chapter is sufficient for all types of circuit simulations.

A common-source (CS) amplifier, shown in Fig. 5.4, is then first tested. CS stage is one of the three basic single-stage CMOS topologies. Circuit parameters W_L
n = _0.510 µm/µm, Lf ict = 100 pH, R = 10 KΩ, Cout = 100 fF, and VDD = 2.5 V are chosen. Vbias is a step

with a magnitude of 1 V and a rise time of 5 ns. Note that a fictitious inductance has to be inserted in series with the branch resistor in order to not violate LIM formulation. The simulation is performed using both model types, and Figs. 5.5 and 5.6 indicate that the two models are well aligned. For the purpose of this simulation, frequency of 300 MHz and time step of 0.1 ps are used.

A simple hand calculation can help us do a sanity check. Assuming the operation in the saturation region, we have

ID = 1 2µnCox W L (VGS− VT) 2 . (5.12)

Given the parameters in Table 4.1, µnCox and VT are roughly 160 µA/V2 and 0.7 V respec-

tively. Substituting these into Eq. (5.12) we get a DC current of 144 µA which leads to transconductance

gm =

2ID

VGS− VT

V

V

V

C

R

V

Figure 5.4: CS amplifier schematic.

Now the DC gain becomes

|Gain| = | − gmR| = 9.6. (5.14)

This agrees with the gain of 8 seen from 5.5 given the simple hand calculation and the rough estimates. Also, we expect the transistor to go into saturation and lose its perfect sine shape as we increase the input voltage Vin. Both of the models capture this effect as shown in

Fig. 5.6.

A comparison between the two models is provided in Figs. 5.7 and 5.8. The quantitative error for an input voltage of 10 mV is as low as 0.2%.

5.2

2-Stage CMOS Amplifier

Another CMOS amplifier, displayed in Fig. 5.9, reassures the viability of the model II as the number of transistors increases. The op-amp is a two-stage system with two power supplies providing ±2.5 V. The current mirror formed by M 5 − M 8 supplies the differential pair M 1 − M 2 with bias current. The W

L

V

V

V

V

I

M1

V

C

M2

M3

M4

M5

M7

M6

M8

Figure 5.9: CMOS amplifier schematic.

differential pair is actively loaded by current mirror M 3 − M 4. The second stage of the op- amp is M 6, which is a CS amplifier for which M 7 is the current source. This op-amp does not have a low output impedance and is thus not suited for driving a low-impedance load. Overall DC open loop gain is approximately 61 dB. Table 5.1 shows the design parameters for the op-amp.

Let Ibias = 90 µA, VT n = 0.7 V, VT p = −0.8 V, µnCOX = 160 µA/V2, µpCOX = 40 µA/V2 and |VA| = 10V.

Table 5.1: CMOS Amplifier Design Parameters M1 M2 M3 M4 M5 M6 M7 M8 W L (µm/µm) 20 0.8 20 0.8 5 0.8 5 0.8 40 0.8 10 0.8 40 0.8 40 0.8 ID (µA) 45 45 45 45 90 90 90 90 |VGS− VT| (V) 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 gm (mA/V) 0.3 0.3 0.3 0.4 0.6 0.6 0.6 0.6 ro (KΩ) 222 222 222 222 111 111 111 111

Since M 8 and M 5 are matched, current through M 5 drain, I, is equal to Ibias; therefore,

M 1, M 2, M 3 and M 4 will have I₂ = 45 µA. Also,

IM 7 = Ibias = 90 µA = IM 6.

From Eq. (5.12) we find VGS− VT, overdrive voltage, for each transistor. Transconductance

is then calculated from gm = _VGS2I_−VD _T. Output resistance is

ro =

|VA|

ID

(5.15)

which is provided in Table 5.1 for all the transistors.

First stage gain = A1 = gm1(ro2||ro4) = 33.3 V/V (5.16)

Second stage gain = A2 = −gm6(ro6||ro7) = −33.3 V/V (5.17)

Overall DC open loop gain = A1A2 = −1109 V/V = 61 dB. (5.18)

Output capacitance is 100 fF and the bias current has a rise time of 5 ns. Fictitious inductance and simulation time step are selected to be 100 pH and 0.1 ps respectively. The transient response at 500 kHz is shown in Fig. 5.10. It is assumed that 500 kHz falls within the op-amp’s 3 dB bandwidth where the DC gain holds. Output voltage in Fig. 5.10 gives

Figure 5.10: Input and output voltages of the CMOS amplifier for f = 500 kHz.

a gain of 920 = 59.3 dB, which very well aligns with our manual calculation.

As the frequency increases, we expect to see a gain drop due to the poles of the system. For a complicated system such as Fig. 5.9, it is a difficult task to find the 3 dB bandwidth since the circuit has loops and many capacitors. Assuming a single-pole system, an unsophisticated estimate would be given by

f3dB =

1

2π (ro6||ro7) Cout

≈ 28 MHz. (5.19)

Figure 5.11: Output voltage of the CMOS amplifier for f = 10 MHz.

28 MHz. Figure 5.11 shows that the gain drops to 50 = 34 dB at frequency of 10 MHz. There- fore, the proposed MOSFET model and its incorporation into LIM are validated through the provided data and the fact that it behaves as expected.

This chapter focused on enhancing the MOSFET model I and introduced the novel model II. We also entered the domain of analog design, and simulation results of analog amplifiers exhibited good correlation with model I. These results illustrate the capabilities of LIM to compete with the existing industry-standard simulation tools.