CONCLUSION AND FUTURE WORK
6.1
Conclusion
In this work, we have demonstrated an extensive methodology to simulate MOSFETs using LIM. Two LIM-based circuit models were presented by making use of the SPICE LEVEL 3 standard. This translates into accounting for the charge storage capacitors as well as boosting the general accuracy. The method captures the dynamic behavior of submicron-technology integrated circuits also observed in commercial simulators.
First, we defined a detailed strategy for modeling SPICE LEVEL 3 in LIM with depletion and channel capacitances. Simulation results of several major logic designs were provided. The accuracy and reliability of the method were verified with the comparisons made with the popular industry standard simulation tools. As already established in Chapter 4 we are convinced that it is safe to conclude that the model is viable for circuits designed in combinational logic.
Next, we introduced a second model to extend the knowledge and address the drawbacks of the previous one. The comprehensive and efficient algorithm was explained. The modularity of the second model allows the incorporation of the transistors in a straightforward manner with a higher performance. In this exercise we decided to further evaluate the study by proceeding with analog designs as well. The model was examined and multiple simulations were executed to validate it.
6.2
Future Work
While we have significantly contributed towards the latency insertion method, and its aug- mentation and marketing as a computer-based analysis tool, there obviously are limitations and points of improvement that must be explored.
Perhaps the prime topic to explore is the employment of BSIM models. In this work we proved the capability of LIM to handle MOSFETs with utilizing a reasonably accurate and robust device model. However, the model is not scalable and the first derivative of drain current is discontinuous. In addition, the model fails to give a good description of a MOSFET when the channel dimension is scaled down. This is essentially the main limitation. Today’s CMOS technologies used in the modern ICs might be as small as tens of nanometer. While SPICE LEVEL 3 is adequate down to 0.5 µm, there is a need for more elaborate models as the technologies move into the deep sub-micron regime. Therefore, future study has to involve incorporating BSIM models into LIM.
Although this work provided the simulation results of the fundamental circuits in both analog and digital designs and confirmed the robustness of LIM, simulation of very large CMOS ICs is yet to be performed. Problems may arise if the number of transistors in the circuit increases dramatically. For instance, simulation of PLL and analog-to-digital converter (ADC) would be a good starting point for future investigations.
Another area of study for future researchers is stability for active circuits such as the ones containing transistors. The primary reason of instability is the transistor gain. An- other major factor behind rising instability in computation is the large number of latency elements present in the circuit and their very small values. The charge storage capacitors of a MOSFET may be as small as tens of femtofarad, meaning that the simulation has to be performed with very small time steps. However, we have not yet developed a procedure to determine the maximum time step for which the simulation remains stable. Hence, exploring general stability criteria for active circuits is crucial.
In addition, the value of the inserted fictitious latencies in the proposed models in Chap- ters 4 and 5 remains undetermined and requires furtherer probing. It would be very valuable if future work developed a fully automated algorithm that specified the optimum fictitious
values that maintain stability without sacrificing much speed. Also, introducing elements into the circuit where originally they did not exist clearly decreases accuracy. Therefore, future research may move in a new direction and implement new models to avoid these drawbacks.
REFERENCES
[1] L. W. Nagel, “SPICE2, a computer program to simulate semiconductor circuits,” May 1975. [Online]. Available: https://www2.eecs.berkeley.edu/Pubs/TechRpts/1975/ERL- 520.pdf.
[2] J. E. Schutt-Aine, “Latency insertion method (LIM) for the fast transient simulation of large networks,” in IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 48, no. 1, Jan. 2001, pp. 81–89.
[3] J. Choi, M. Swaminathan, N. Do, and R. Master, “Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method,” IEEE Trans- actions on Electromagnetic Compatibility, vol. 47, no. 3, pp. 424–439, Sep. 2005. [4] T. Sekine and H. Asai, “CMOS circuit simulation using latency insertion method,”
in Proceedings of the Electrical Performance of Electronic Packaging Conference, 2008 IEEE-EPEP.
[5] P. Goh and J. E. Schutt-Aine, “Latency insertion method (LIM) for CMOS circuit sim- ulations with multi-rate considerations,” in Proceedings of the Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference, pp. 125–128. [6] Y. Hizawa, H. Kurobe, T. Sekine, and H. Asai, “Nonlinear block latency insertion method for fast simulation of strongly coupled network with CMOS inverters,” in Proceedings of the Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE, pp. 1–4.
[7] J. E. Schutt-Aine and P. K. Goh, “Phase-locked loop simulations using the latency insertion method,” in Proceedings of the Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium.
[8] T. Sekine and H. Asai, “Application of latency insertion method to CMOS circuit simulation,” NOLTA2008, Sep. 2008.
[9] A. Vladimirescu and S. Liu, “The simulation of MOS in- tegrated circuits using SPICE2,” Oct. 1980. [Online]. Available: https://www2.eecs.berkeley.edu/Pubs/TechRpts/1980/9610.html
[11] H. Shichman and D. A. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits,” IEEE J. Solid-State Circuits, vol. 3, no. 3, pp. 285–289, Sep. 1968.
[12] Virtuoso Advanced Analysis Tools User Guide, Cadence, Berkshire, U.K., 2008. [Online]. Available: http://www.cadence.com.
[13] Star-Hspice Manual, Avant!, 1998. [Online]. Available: https://web.engr.oregonstate.edu/ moon/ece323/hspice98/
[14] P. K. Goh, “A fast multi-purpose circuit simulator using the latency insertion method,” Ph.D. dissertation, Univ. of Illinois at Urbana-Champaign, Tech. Rep. UILU-ENG- 2012-2503, Apr. 2012. [Online]. Available: http://emlab.uiuc.edu/jose/theses.html [15] T. M. Comberiate, “Using x-parameters for signal integrity applications,” Ph.D.
dissertation, Univ. of Illinois at Urbana-Champaign, Dec. 2013. [Online]. Available: http://emlab.uiuc.edu/jose/theses.html
[16] Z. Deng and J. E. Schutt-Aine, “Stability analysis of latency insertion method (LIM),” in Proceedings of the 14th Topical Meeting on Electrical Performance of Electronic Pack- aging (EPEP), Portland, OR, Oct. 2004.
[17] J. E. Schutt-Aine, “Stability analysis for semi-implicit LIM algorithm,” in Asia Pacific Microwave Conference, 2009, pp. 1270–1272.
[18] I. N. Hajj, “Computational methods in circuit simulation,” unpublished.
[19] Y. Tsividis, “Problems with precision modeling of analog MOS LSI,” in International Electron Devices Meeting, Dec. 1982, pp. 274–277.
[20] T. Yuan and T. H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed. Cambridge University Press, 1998.
[21] E. H. Nicollian and J. R. Brews, MOS(Metal Oxide Semiconductor) Physics and Tech- nology. Wiley, 2002.
[22] B. Sheu, D. Sharfetter, P. Ko, and M. Jeng, “BSIM: Berkeley Short Channel IGFET Model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 558–566, 1987.
[23] P. Allen and D. Holberg, CMOS Analog Circuit Design, 2nd ed. Reading, MA: New York: Oxford University Press, 2002.
[24] Virtuoso Simulator Components and Device Models Reference Product Version 11.1, Sep. 2011, pp. 1129–1241. [Online]. Available: http://www.cadence.com.
[25] W. Liu, MOSFET Models for SPICE Simulation Including BSIM3v3 and BSIM4. New York : Wiley-Interscience Publication, 2001.
[26] W. Liu et al., BSIM3v3.3 MOSFET Model User’s Manual, Univ. Califor- nia, Berkeley, 2005. [Online]. Available: http://ngspice.sourceforge.net/external- documents/models/bsim330 manual.pdf.
[27] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Prentice Hall, 2003.