Comparator

6.6.1. Comparator Architecture

The comparator that was modeled is shown in Figure 32. The outputs from the sense amplifiers are connected to the inputs labeled b_nand b_n-bar. The a_nand a_n-bar inputs are driven by tag bits in the address. Initially, the output of the comparator is precharged high; a mismatch in any bit will close one pull-down path and discharge the output. In order to ensure that the output is not discharged before the b_nbits become stable, node EVAL is held high until roughly three inverter delays after the generation of the b_n-bar signals. This is accomplished by using a timing chain driven by a sense amp on a dummy row in the tag array. The output of the timing chain is used as a "virtual ground" for the pull-down paths of the comparator. When the large NMOS transistor in the final inverter in the timing chain begins to conduct, the virtual ground (and hence the comparator output if there is a mismatch) begins to discharge.

6.6.2. Comparator Delay

Since we assume that the a_nand b_nbits will be stable by the time EVAL goes low, the critical path of the comparator is the propagation delay of the timing chain plus the time to discharge the output through the NMOS transistor in the final inverter.

First consider the timing chain. The chain consists of progressively larger inverters; we as- sume that size of each stage is double the size of the previous stage (see Appendix I). Each stage can be worked out using a simple application of Horowitz’s approximation described in Section 5.5:

a₀ 0 b a₀ 0 b b a b a b a b 1 1 ₁ a 1 n n n n Vdd PRECHARGE OUT large n small p From dummy row sense amp in tag array EVAL Figure 32: Comparator

t_f,1 = res_p,on( W_compinvp1)×[ gatecap( W_compinvn2+ W_compinvp2, 10) +

draincap_p( W_compinvp1, 1 ) + draincap_n( W_compinvn1, 1 ) ]

t_f,2 = res_n,on( W_compinvn2)×[ gatecap( W_compinvn3+ W_compinvp3, 10) +

draincap_p( W_compinvp2, 1 ) + draincap_n( W_compinvn2, 1 ) ]

t_f,3 = res_p,on( W_compinvp3)×[ gatecap( W_evalinvn+ W_evalinvp, 10) +

draincap_p( W_compinvp3, 1 ) + draincap_n( W_compinvn3, 1 ) ]

T_comp,1 = delay_fall( t_f,1, tfall_sense,tag, v_thcompinv1, v_thcompinv2)

T_comp,2 = delay_rise( t_f,2, , vtf,1 _thcompinv2, v_thcompinv3)

v_thcompinv2

T_comp,3 = delay_fall( t_f,3, , vtf,2 _thcompinv3, v_thevalinv) 1−v_thcompinv3

The final stage involves discharging the output through a pull-down path and the NMOS tran- sistor of the final inverter driver. An equivalent circuit is shown in Figure 33. The resistance R_evalnis the resistance of the pull-down transistor in the final inverter:

R_evaln = res_n,switching( W_evalinvn)

In the worst case, only one pull-down path is conducting; the resistance R_pulldown is the path’s equivalent resistance. Since it was assumed that the inputs are stable when the evaluation takes place, we are interested in the full-on resistance of the pull-down path:

R_pulldown = 2 res_n,on( W_compn)

In Figure 32, it is clear that approximately half of the capacitance is on the input side of the pull-down path, and half is on the output side. These capacitances will be denoted by C_eqbotand C_eqtop. The first can be written as:

R_evaln C_eqtop C eqbot R pulldown out

Figure 33: Comparator equivalent circuit C_eqbot = tabits ×[ draincap_n(W_compn,1) + draincap_n(W_compn,2) ] +

draincap_p( W_evalinvp, 1 ) + draincap_n( W_evalinvn, 1 )

where tagbits is the number of tag bits (from Equation 16). Note that there are 2×tagbits pull- down paths (two for each bit); half of the "off" paths have the top transistor off, and half have the bottom transistor off. We have also included the drain capacitances of the final inverter stage.

The capacitance C_eqtopcan be written similarly:

C_eqtop= tabits ×(draincap_n(W_compn,1) + draincap_n(W_compn,2)) + draincap_p( W_compp, 1 ) +

gatecap ( W_muxdrv1n+ W_muxdrv1p, 20 ) + tagbits ×N_tblN_tspdC_wordmetal

The output capacitance is taken to be the input capacitance of either the multiplexor driver described in Section 6.7 or the valid signal driver in Section 6.9 (the first stage of both structures are the same, so they have the same input capacitance). We have also included metal capacitance of the metal output (it is assumed that the metal crosses the entire width of the tag array).

The circuit in Figure 33 is equivalent to the circuit in Figure 21, so the same solution can be used. The result is:

(31)

T_step= [ R_evalnC_eqbot+ ( R_evaln+ R_pulldown) C_eqtop] ln ( 1 )

v_thmuxdrv1

The non-zero input fall time can be taken into account using the same method as Section 6.4. There are two possible equations; which one should be used depends on the slope of the input. For a slow rising input:

T_eval = −2 ( vs−vt) +√4 ( vs−vt) 2_−4×m×c 2×m (32) where c = ( v1 _s−v_t)2 − 2 T_step( V_dd−V_t) m

and m is the slope of the input waveform:

m = Tcomp,3 v_thevalinv

m < Vdd−Vt

2 T_step

For a quickly rising input (m greater than Vdd−Vt):

2 T_step

T_eval = T_step + Vdd+ Vt − 2 m

v_s

m (33)

The above equations can be combined to give the total delay due to the comparator:

T_compare = T_comp1+ T_comp2+ T_comp3+ T_eval (34)

6.6.3. Hspice Comparisons

Figure 34 compares the analytical model to a Hspice model of the circuit. As can be seen, there is good agreement between the two models.

Compare Delay Tag Bits 0ns 1ns 2ns 3ns 4ns 0 10 20 30 40 . . . . g g Analytical Hspice g . . ..g. . . . . ... . .g . . ..g. . . . . ..g. . . . . ..g. . . . . ..g. . . . . ..g. . . . . ..g. . . . . ..g. . . . . ..g

Figure 34: Comparator delay