Comparison of PCM properties with those of other memory technologies

The driving factor behind the significantly increasing research efforts in exploring novel devices for data storage can be understood from the following perspectives:

1.4. Phase-Change Memory Technology

• From the system point of view, the performance of the processor is increasingly limited by the access time between the processor and the memory unit. The power consumption of such memory sub systems is also critical in the design and operation of such systems. • In the past decade, the proliferation of Flash-based memory systems in both the enter- prise and consumer-grade storage space has highlighted the huge potential for high- capacity and high-speed memory technology in the memory hierarchy. The potential replacement of hard-disk drives (HDD) by Flash for selective applications supports this claim.

• As the need for high-capacity, high-performance storage systems keeps increasing because of the evolving big-data applications, even the universal Flash memories will not be able to meet the growing requirements owing to the scalability limitations of Flash.

Hence, any emerging technology should be able to address all the above-mentioned issues for it to be considered as a potential replacement for existing technologies. Therefore, the success of these emerging technologies depends on how well they perform compared with the current technology. In most cases, there should be remarkable performance improvement as the potential replacement would mean considerable modifications to the already existing storage system space. Table 1.2 summarizes the comparison of PCM with other existing memory technologies [Eilert et al., 2009]. Given that the characteristics of PCM most closely approximate that of the dynamic random access memory (DRAM) and the Flash memory, it exactly falls into the class of SCM memory technology. Therefore, it is worthwhile to briefly compare the properties of PCM with those of the currently predominant memory technologies, DRAM and Flash.

1.4.5.1 PCM vs. Flash storage

As discussed in Section 1.2.2.1, there are two kinds of Flash memories, NOR and NAND. NAND flash can be packed more densely than NOR flash, and though NOR flash offers fast random access its programming throughput is much lower than that of block-based NAND memory architectures. NAND memory is a high-density, block-based architecture with slower random access that is mainly used for mass storage applications.

The read/write endurance for both NOR and NAND is around 20 k–30 k cycles. In the sub 20 nm regime, the endurance is only around 5 k–10 k cycles. The properties of Flash are well within the reach of PCM capabilities. NOR Flash with its floating-gate technology has reached its scalability limits, mainly because of the difficulties in scaling the thickness of the tunnel oxide.

Thus PCM can be considered as a potential replacement for NOR flash in the near future. In contrast, replacing NAND flash is much harder, at least for the current trends of PCM, despite

Chapter 1. Introduction

Attributes PCM DRAM NAND HDD

Non-Volatile Yes Yes Yes Yes

Cell Area 6-8F2 4F2 5F2 —

Erase Required Bit Bit Block Sector

Software Simple Simple Complex Simple

Power ≈100−500 mW/die ≈W/GB ≈ 100 mW/die ≈10 W Write Bandwidth 1−100+ MB/s/die ≈GB/s 1−100 MB/s/die 200−400 MB/s

Write latency ≈200−1000 ns ≈20−50 ns ≈100 μs ≈10 ms Read latency 50−100 ns 50 ns 10−25 μs ≈10 ms

Idle power 0.1 W ≈W/GB 0.1 W ≤10 W

Endurance 108 ∝ 104− 105 ∝

Data retention Not f (cycles) ms f (cycles) Not f (cycles) Table 1.2: Comparison of PCM technology with the currently predominant memory technolo- gies in the memory hierarchy [Eilert et al., 2009]. The characteristics of PCM most closely approximate those of dynamic random access memory (DRAM) and Flash memory.

its superiority in both endurance and read performance. The cost criterion is the biggest challenge, as NAND flash is mainly used in consumer electronic devices, where cost is of serious concern. In spite of the scalability limits, the memory density of NAND Flash can further be improved by the trap storage technology and possibly 3D integration [Choi and Park, 2012; Kim et al., 2012]. In terms of MLC realization, NAND has been shipping 2-bits/cell for years and even 3-bits/cell more recently, albeit with much lower endurance.

PCM with its wide resistance range is capable of MLC operation. PCM with 2-bits/cell have already been demonstrated, although on a smaller scale [Close et al., 2013]. Although the write operations are slow for NAND flash, impressive write data-rates can be achieved as its low write power allows the programming of many bits in parallel. Parallel programming is limited by the power requirements for PCM programming. Overall, PCM has three major advantages over flash technology:

• Better scalability - PCM is scalable friendly and offers better reliability at lower technol- ogy nodes. Data retention in Flash decreases significantly with the scaling of gate-oxide thickness.

• Faster Write - Faster programming bandwidths can be achieved in PCM than in Flash. With PCM, a cell can be written repeatedly without any intervening operations. In contrast, a programming operation in flash requires the corresponding cell to be erased before programming. This contributes to a major performance decrease for random 20

1.4. Phase-Change Memory Technology

write operations. Typical Flash programming times are in the order of milliseconds, whereas they are on the order of few hundreds of nanoseconds in PCM.

• Endurance - The endurance of PCM is several orders of magnitude higher than that of flash. Also unlike the Flash, the data retention of PCM is independent of the endurance cycling.

1.4.5.2 PCM vs. DRAM

Although PCM is a non-volatile memory technology, it is worthwhile comparing it with volatile memory technologies (such as SRAM and DRAM), as PCM is considered to be one of the top contender for storage class memory. A typical SRAM cell uses six CMOS transistors to store each memory bit and occupies more than 120F2in chip real estate1per bit which is much larger than a PCM cell [Burr et al., 2010]. SRAM cells are widely used in cache memories, where they typically run at the CPU clock speed, so that the access time must be less than 10 ns. The access time of PCM is limited by its write speed (SET pulses), which depends on the crystallization speed of the phase-change material. Although, some researchers have demonstrated the use of SET pulses shorter than 10 ns [Bruns et al., 2009], more realistic large- array demonstrations tend to require SET pulses that range from 50 to 500 ns in duration. Both PCM and DRAM are power-hungry technologies. The power-hungry nature of DRAM is not solely due to its periodic refresh, which takes place only infrequently, while compared to the achievable data rate. Instead, the power inefficiency in DRAM is due to the simultaneous addressing of multiple banks within the chip. In DRAM, there is an inherent need to re-write the data after each read access. Thus simply by being non-volatile, PCM could potentially be an alternative, albeit at longer latency to DRAM, despite the inherently power-hungry nature of PCM write operations. In the case of stand-alone memories, the cost is directly proportional to memory cell size. State-of-the-art DRAM cells occupy 4F2in chip area. Such small cell sizes have already been demonstrated in PCM using a diode as access device. PCM also competes favorably with DRAM in terms of scalability in future generations, as DRAM developers are quickly hitting various scaling limits associated with storage interference, device leakage, and challenges in integrating high aspect-ratio capacitors in tight spaces. Currently, DRAM has fallen behind NAND Flash and standard CMOS logic technologies in terms of scaling to the 32-nm technology node and preparation for the sub 20-nm node.

1.4.5.3 PCM as Storage Class Memory

Given the present scenario, PCM is the most promising NVM technology for storage class memory. It has been projected that initially the cost per bit for PCM will be much higher than that of disks and comparable to that of flash. Thus, it will be used in systems in which size (e.g.,

1_{Semiconductor device technology node is commonly described by the minimum feature size F that is available} via lithographic patterning. This measure of device size is independent of the particular device technology used to fabricate the memory.

Chapter 1. Introduction

in mobile devices), performance, and/or reliability in harsh environments are paramount. Soon, the cost per bit will decrease and will approach that of disk drives. This is possible, as the memory density of PCM can be increased using the methods discussed earlier.