at the 45 nm technology node, and has also been projected, through models and simulations, to not pose a serious threat at future, sub-20 nm technology nodes [Russo et al., 2008].
5.1.4 Read disturb
Apart from spontaneous crystallization, the other mechanism that can influence crystallization and induce data loss is repeated read operations. During every read operation, the small read current flowing through the device can induce a localized heating that can accelerate the spontaneous transition from amorphous to crystalline, thus inducing a premature fault. As the crystallization process of the amorphous phase is promoted at higher temperatures, these failure mechanisms are aggravated at elevated temperatures [Sebastian et al., 2015].
Given the typical reliability concerns for MLC operation in PCM, it is interesting to study each of the MLC-enabling technologies (described in Section 4.3) offering resilience to drift and variability in terms of the MLC reliability criteria, such as temperature fluctuations and endurance cycling.
5.2 Experimental Characterization of MLC PCM
The choice of phase-change material, the design and fabrication of the memory device, including the process definition and the material deposition technique, are key components in demonstrating the reliability and endurance performance for MLC operation. Mushroom-type memory devices with doped-GST as phase-change material are used for the experiments. The bottom electrode is formed by a lithographically independent, so-called “key-hole” process [Breitwisch et al., 2007], creating the keyhole with a sub-lithographic CD that is essentially independent of the original feature size. The keyhole is subsequently filled with TiN, which acts as the heater (bottom electrode).
The PCM devices are integrated into a prototype chip serving as the characterization test- vehicle in 90 nm IBM9SF CMOS technology. Our experimental hardware platform is built around the prototype PCM chip with a 2×2 M cell array with a 4-bank interleaved architecture (Fig. 5.2). The memory array size is 2×1000 μm × 800 μm. In addition to the PCM cell array, the prototype chip contains the necessary circuitry for cell addressing, on-chip ADC for cell readout and voltage- or current-mode cell programming [Close et al., 2010]. Table 5.1 summarizes the specifications of the PCM prototype chip.
5.2.1 Characterization Platform
Figure 5.3 illustrates the schematic block diagram of the versatile hardware platform designed for high-performance characterization and testing of non-volatile memories. The platform is based on a reconfigurable hardware/software architecture with a high degree of multi- domain testing and data-acquisition capabilities and is closely based on the one proposed
Chapter 5. Reliability and data retention analysis in MLC PCM
Figure 5.2: Die micrograph of the prototype memory chip used in the experiment. The PCM chip consists of a 2×2 M cell array with a 4-bank interleaved architecture.
Table 5.1: Specifications of the PCM prototype chip
CMOS baseline 90-nm, 6 metal levels of Cu
Access device NMOS
Memory element Doped Ge2Sb2Te5(d-GST)
Array size 2×2 M cells Supply voltage 2.5 V ADC resolution 8 bits Readout latency 500 ns
in [Papandreou et al., 2013]. It provides a valuable tool for statistical characterization of the solid-state memory channel for new and emerging non-volatile memories. It consists of the following main units:
• A high-performance analog-front-end (AFE) board that contains a number of digital-to- analog and analog-to-digital convertors (DACs and ADCs) along with discrete electron- ics, such as power supplies, voltage, and current reference sources, etc.
• A FPGA board that implements the data acquisition and the digital logic to interface with the memory device under test, with all the electronics of the AFE board.
• A second FPGA board with an embedded processor and Ethernet connection that implements the overall system control and data management as well as the interface with the data processing unit.
• A temperature control unit consisting of a Eurotherm temperature controller, a temper- ature sensor, a heating resistor and the power supply.
• A workstation with MATLAB running a lab automation test suite for executing numerous experimental scenarios and providing real-time data processing.
5.2. Experimental Characterization of MLC PCM Temperature Control Prototype PCM Chip Oscilloscope ADC & DAC Units FPGA Hardware Modules AFE Circuitry Voltage and Current References Embedded processor Ethernet MAC/PHY User Interface MATLAB Ethernet MAC/PHY FPGA Board II and base board FPGA Board I
TCP/IP TCP/IP
Serial Port
Figure 5.3: Schematic block diagram of the complete hardware characterization platform.
NVM support board ADC units Power supply units DAC units REF units FPGA board #2 FPGA board#1
Chapter 5. Reliability and data retention analysis in MLC PCM
The prototype PCM chip is connected to the hardware characterization platform via a specially designed chip support board that offers numerous test-point buffers enabling external access to the chip’s critical internal signals for debugging and monitoring purposes. The lab automa- tion test suite also provides the necessary interface to the platform’s temperature control unit for variable high-temperature characterization experiments. The temperature of the device under test is measured using the temperature sensor attached underneath the chip. A heater with 20 W power is also mounted along side the temperature sensor. The PID temperature controller monitors the input from a temperature sensor and provides a power output through the power supply to the heating element. The overall chip temperature can be increased by applying power to the heater.
5.2.2 Experimental Procedure
Figure 5.5 depicts the flow chart of the experimental procedure that was designed to assess the MLC reliability of the PCM prototype chip in terms of data retention and cycling endurance under variable time and temperature conditions. A sub-array of 64 k pristine memory cells is selected and subjected to repeated SET/RESET programming cycles. During the endurance cycling, single RESET/SET pulses are used to repeatedly program and erase the cells. The cycling RESET pulse is a box-type pulse of maximum power and a width of 150 ns. The cycling SET pulse is of moderate power with a trailing edge of 2.4μs. At regular intervals in a logarithmic fashion, i.e., every 104cycles, 105cycles, etc., endurance cycling stops and the cells are analyzed in terms of MLC programming and data retention under variable time and temperature profiles.
More specifically, the sub-array is programmed into four distinct resistance levels, namely,
L0 (SET), L1, L2 and L3 (RESET). The two intermediate levels, L1 and L2, are programmed
using the iterative programming algorithm. The maximum number of iterations allowed during the iterative programming operation was set to 20. The two corner levels, L0 and L3, are programmed by single SET and RESET pulses, respectively. The stored levels are based on random user patterns encoded by the scheme described in Section 4.3.4.
After the successful programming of the cells under test, the stored data in the sub-array is read back at regular intervals to evaluate the drift performance of the various read-out metrics described in Section 4.3.3. To assess the bit-error performance under practical operating conditions and to study the drift behavior at elevated temperatures, a profile in which the temperature is varied between 30◦C and 80◦C was used. The temperature profile over time is illustrated in Fig. 5.11(a). After the retention measurements, the cycling continues to the next cycling point. This procedure continues for a total of 1 million (106) cycles.
The two intermediate levels (L1 and L2) are optimally placed for each of the R- and eM -metrics before programming in order to maximize retention for the given temperature profile and readout metric.