The CPM receiver literature typically expresses branch metric complexity as the number of matched filters. The phase rotation computations are ignored [28] [32] [34]. In this thesis we focus on implementation and so a more ap- propriate measure of complexity is real valued multiplications (and adds) per decoded symbol. By taking account of the symbol rate an even more useful metric is multiplications per second and additions per second. These metrics do not account for filter coefficient word-length nor received signal sample word-length. We account for that in a later section by expressing complexity directly in terms of FPGA resources.
The maximum-likelihood receiver calculates branch metrics according to Equation (5.1), previously presented in section 2.4.
Zn(αn, θn) =<{e−jθn
Z (n+1)T
nT
˜
r(t)e−jθ(t,αn)dt} (5.1) Express in terms of real operations only by substitutingr˜(t) =rI(t)+jrQ(t)
into Equation (5.1) we get Equation (5.2) [6].
Zn(αn, θn) = cos(θn)[ Z (n+1)T nT rI(t) cos(θ(t, αn))dt+ Z (n+1)T nT rQ(t) sin(θ(t, αn))dt] + sin(θn)[ Z (n+1)T nT rQ(t) cos(θ(t, αn))dt− Z (n+1)T nT rI(t) sin(θ(t, αn))dt] (5.2) Each integral represents a matched filter. cos(θ(t, αn)) and sin(θ(t, αn))
are the matched filter coefficients where αn is an L length symbol sequence.
5.2. COMPUTATION COMPLEXITY 49
h p L M N R (1/T) Branch Metric multiplies/s
Branch Metric adds/s
1/4 8 3 4 2 27 MSamples/s 6.9 GMults/s 3.5 GAdds/s Table 5.1: CPM Branch Metric Filter Bank Complexity
matched filters. However, everyαnsequence has a corresponding negative se-
quence and using the trigonometric identities in Equation (5.3), the number of matched filters is halved. The maximum-likelihood branch metric filter bank is2MLmatched filters [6].
cos(A) = cos(−A)
sin(A) =−sin(−A) (5.3) cos(θ(t, αn))andsin(θ(t, αn))are precomputed filter coefficients. Each inte-
gral (filter) requires N real multiplications and N-1 additions, where N is the number of samples per symbol. For a symbol rate ofR= 1/Tsymbols/s where T is the symbol period, Equation (5.4) describes the matched filter multiplica- tion complexity and Equation (5.5) is the matched filter add complexity. Table 5.1 shows this complexity for the CPM configuration selected in Chapter 3.
M atchedF iltersmultiplies/s=R2MLN (5.4)
M atchedF iltersadds/s =R2ML(N−1) (5.5)
To achieve these high computational rates, a traditional solution might use the embedded multipliers now present in the fabric of modern low-cost FP- GAs. The XC3S1800A-DSP Spartan 3A-DSP FPGA is the largest Xilinx FPGA that meets the cost requirements for this application. This part has 84 multipli- ers in addition to the general purpose LUT and flip-flop fabric. These multipli- ers can be clocked at a maximum of 250 MHz which provides for a processing capability 21 giga-multiplies/s [44].
At a first analysis it appears that the embedded multipliers have the mul- tiplication capacity to support the matched filter processing. However, Equa- tion (5.4) and Table 5.1 ignore the phase rotation multiplications. Ultimately there are pML/2 (256) unique branch metrics to be calculated yet there are
only 84 multipliers available. With 128 matched filters, the processing might be arranged such that each embedded multiplier performs the processing for 2 matched filters. This requires the two results per multiplier to be stored adding further complexity. A solution using the majority (76%) of the available multi- pliers is undesirable since other parts of the CPM receiver also require the use of the multipliers. For example, front end adjacent channel filtering and the adaptive equaliser.
In some respects the Xilinx datasheet claim of 21 giga-multiplies/s over- states the devices capability. Firstly, every clock cycle must be used to generate a result. This requires extra logic to sequence operands and store results. And secondly, the multipliers must be clocked at their maximum rate of 250 MHz and the design must meet timing. Getting data into and out of the multipliers from the general logic fabric at this rate is a design challenge. Furthermore, it is unlikely other parts of the FPGA design would operate at this frequency and
so extra logic and complexity is required to transfer the data between this high speed 250 MHz clock domain and the rest of the design.
The phase state rotation complexity can be reduced and almost eliminated for some specific values of h. For example, with h=1/4 there are 8 phase states, yetcos(θ(t, αn))and sin(θ(t, αn))take on values of 0,1 or +- 0.707 only. Mul-
tiplication by 0 and 1 is trivial so the multiplication by 0.707 is the only one required per matched filter output. This thesis proposes an implementation that ignores this optimisation and so it is generalised for any h, L, and M.
5.3
Applying Distributed Arithmetic to a CPM Fil-
ter Bank
The microwave radio application considered in this thesis requires a symbol rate of 27 MSymbols/s. This is almost an order of magnitude less than clock rates achievable in current generation low cost FPGAs. For example, the Spar- tan 3A-DSP FPGA multipliers support operation at up to 250 MHz[44] and as shown in section 5.4.3, clock rates above 200 MHz are achievable in the FPGA logic fabric. The implementation proposed by this thesis exploits this by car- rying out the processing in a bit-serial fashion using a well known technique called distributed arithmetic.
Distributed arithmetic (DA) filters are a logic resource efficient way of im- plementing a finite impulse response (FIR) filter [47] [48]. The signal to be filtered is passed to the filter in a bit-serial fashion, least significant (LSB) first. This requires a system clock at a rate several times that of the incoming sample rate. In this way, a higher system clock is traded off against lower hardware costs. In our application we have a symbol rate of 27 MSymbols/s and Spartan 3ADSP clock rates of more than 200 MHz are achievable, making DA filters attractive for this application.
A distributed arithmetic filter implements the standard FIR filter equation precisely. Equation (5.6) describes aM tap FIR filter with filter coefficientsh(k) and input signalx(m)where m is the discrete time variable [47].
y(m) =
M−1
X
k=0
x(m−k)h(k) (5.6) The key to applying this to a CPM branch metric filter bank is to bring the phase rotations inside the integral and combine the in-phase and quadrature matched filters into a single filter. This is shown starting with Equation (5.7) and ending in Equation (5.8) where the branch metrics computations are ex- pressed in a sum of products form that is equivalent to Equation (5.6).
Zn(αn, θn) =<{e−jθn Z (n+1)T nT ˜ r(t)e−jθ(t,αn)dt} =<{ Z (n+1)T nT ˜ r(t)e−j(θ(t,αn)+θn)dt} = Z (n+1)T nT rI(t) cos[θ(t, αn) +θn] +rQ(t) sin[θ(t, αn) +θn]dt (5.7)