“Secure computing” is more of a buzz phrase than ever, and Intel has a plan of its own for how to accomplish that. One of the features to coincide with the release of the new Core processors are chipsets that include the LaGrande tech- nology, a set of provisions to secure a computer from the hardware on up. This includes, among other things, the ability to run applications in entirely isolated environments (making it impossible to hijack or spy on them); encrypted storage that is keyed to a specific computer; pro- tected graphics and I/O; protected appli- cation launching; and “attestation,” which is a way to determine that the LaGrande system is itself running properly.
LaGrande isn’t something everyone will want, and to that end, it’s being marketed as a specialty product for institutions and governments—at least at first. Intel states in its architectural documentation that you not only need a processor and chipset that supports LaGrande, but peripherals, graphics hardware, and a device called the Fixed Token that provides the crypto- graphic keys that LaGrande uses. All of this is guaranteed to cost extra.
The benefits are obvious, but there are just as many risks. Will future PCs come with LaGrande-type technologies as a mandatory add-on to enforce copy pro- tection due to pressure from advocacy groups? Will LaGrande make it more difficult for whistleblowers to report cor- porate malfeasances? Even before it’s actually been rolled out, it’s clear that LaGrande will create at least as many thorny issues as it solves. ▲
supported since SP2 and in Windows Server 2003 SP1 and the SSE4 instruc- tion set. Originally called TNI, or Tejas New Instructions, SSE4 is the newest iter- ation of a set of processor features used to accelerate common math operations, and it also requires support from the OS and applications to use properly.
s p o t l i g h t
Virtualization Technology. Putting multiple CPU cores in a single processor die was only the beginning. The next step up from that is allowing multiple OSes to run side by side. That’s what VT, or Virtualization Technology, promises. VT is an implementation of a methodology, known in its development days at Intel as Vanderpool, that lets the CPU run multi- ple OSes at once with virtually no com- putational overhead.
Current processors are already doing this sort of thing in software, including Microsoft Virtual PC/Virtual Server, VMware, and the open-source hypervisor application Xen all doing this. But the software techniques used cause the OSes to take a performance hit, as much as 10% or more. VT aims to let these things
occur with no perceptible decrease in per- formance. This would let someone, say, replace several existing Intel x86-based servers with one Intel Core server, run- ning a virtual copy of each original server’s OS side by side.
The current release of Xen (which is Linux-only) already supports Intel VT, and plans are on the table for Virtual PC and VMware to support it, too. AMD has a similar technology in the works code- named Pacifica, but the Vanderpool and Pacifica implementations of VT aren’t compatible; you need to implement them differently for each processor.
Macro-Ops Fusion. One of the ways Intel has consistently looked at getting more out of every processor is by having it do more things at the same time, such
The LaGrande security technology, which works with Core processors that feature it, can allow different aspects of a computer (kernel, applications, and memory) to be segregated from each other and policed. In order for the system to be completely effective, though, it requires a computer that has been engineered with LaGrande in mind from end to end. (Source: Intel)
The Intel Core Duo
as process more instructions, fetch more memory for local caching, etc. Macro- Ops Fusion is Intel’s term for a new Core technology that allows two x86 instruc- tions to run as a single internal instruc- tion. This would let the CPU optimize the running of legacy x86 instructions as much as possible, and because there’s no sign that 32-bit x86 code will go away any time soon, this is highly useful.
Reduced power consumption. One other key feature that Intel is stressing hard with Core is reduced power con- sumption. AMD has long been touting the value of CPUs that use less wattage, and Intel is following suit. Conroe uses about 65W by default, but the single-core Millville is only 31W, and Merom for notebooks and tablets only uses anywhere from 35 to 15W. There’s even an ultra- low-voltage version of the Core lineup in the offing, which would use as little as 1 to 5W at a bit of a performance hit, but less than you might expect for something that economical.
Taking The Wrong Bus?
The one area where Intel may run into a serious future performance-stumbling block is how the Core processors deal with memory. The path from a comput- er’s memory to the CPU is notoriously slow; a good deal of a processor’s wasted
time is spent waiting around for the memo- ry to respond. There have been numerous ways to speed this up, including placing L1 and L2 caches of memory directly on the CPU or speeding up the pathway from the processor to the memory.
AMD took the latter approach and created the interconnect HyperTransport system to lessen the latency between mem- ory and CPU. Intel, however, still uses the older FSB technology for memory access. The problem with the FSB is that it also provides a data pathway for other compo- nents, so it’s shared with other things and consequently slower overall.
To make up for this, Intel plans to run the FSB as fast as possible: 1,066MHz for the basic Conroe version of Core 2, 1,333MHz for the higher-end Woodcrest server processors, and 667MHz for Merom. Intel is also using a large on-die L2 processor cache—2MB minimum across the Core—to make up for any laten- cy to memory. The L2 cache is also shared across both cores; if each core needs to access the same bit of cached memory, they can both do so without having to make a roundtrip to system memory. The caching between cores can also be balanced, a tech- nique Intel called Advanced Smart Cache.
So far these strategies for lessening the FSB’s bottlenecks may be paying off. AnandTech.com ran tests of the Core 2 Extreme X6800 (a Conroe CPU with 4MB L2 cache running at 2.93GHz) as compared against an AMD Athlon 64 FX-62 (2.8GHz with 512KB L2 cache). The site found that while memory latency (as measured with ScienceMark 2.0) between the two processors was compara- ble, the memory bandwidth for the Core 2 was only about 65% of the bandwidth of the FX-62. In terms of real-world per- formance, the Core 2 consistently beat the FX-62 in many popular applications, from content creation to games, and by a fairly wide margin.
That said, these tests were only con- ducted on computers with one physical processor. AMD/HyperTransport may prove the better choice over Core 2 machines with multiple physical proces- sors (as opposed to multiple cores on one processor). The good news is that
multiple cores on one processor may be the default in the future, so for most peo- ple the Intel Core 2 may prove the better practical solution after all.
In fact, Intel may already be readying for a transition to a new bus technology, but the details are sketchy at best. One thing that has been announced for the Tigerton—a Core-based, Xeon-grade serv- er processor expected in 2007—is “a new, high-speed interconnect.” However, Intel spokesman Scott McLaughlin stated in an interview reported around the Web that the new interconnect is designed more to connect multiple physical processors to each other rather than provide dedicated memory lanes, so it seems to be primarily for server environments anyway.
Conclusions
The Core has incredible promise, some of which is already being fulfilled. It shows a genuinely new direction for Intel, away from the old formula of “more and faster.” It’s also heartening to see Intel pay more attention to reduced power usage, something becoming more urgent as ener- gy costs climb.
Still, to make sure the Core can really shine, Intel can and should also do away with as many legacy structures as it can, such as depending on the FSB for memo- ry access—something third parties have urged it to do, as well. Here’s hoping it keeps evolving. ▲
by Serdar Yegulalp
Processor Fab Process Cores L2 Cache Speed Wattage Desktop Processors Conroe 65nm 2 4MB 1.6 to 2.67GHz 65W Conroe XE 65nm 2 4MB 2.4 to 2.67GHz 80W Allendale 65nm 2 2MB 1.6 to 2.4GHz 65W Millville 65nm 1 2MB 1.6 to 2.4GHz 31W Wolfdale 45nm 2 3MB 1.6 to 2.4GHz 65W Kentsfield 65nm 4 8MB 1.6 to 2.4GHz N/A Yorkfield 45nm 8 12MB 1.6 to 2.4GHz N/A Ridgefield 45nm 2 6MB 1.6 to 2.4GHz 31W Perryville 45nm 1 2MB 1.6 to 2.4GHz 15W Notebook Processors Merom 65nm 2 2 to 4MB 1.6 to 2.3GHz 35W Penryn 45nm 2 3 to 6MB 1.6 to 2.3GHz 35W Perryville 45nm 1 2MB 1.6 to 2.3GHz 15W Server/Workstation Processors Woodcrest 65nm 2 4MB 1.6 to 3GHhz 65W Clovertown 65nm 4 8MB 1.6 to 3GHhz 80W Tigerton(1) 65nm 4 8MB 1.6 to 3GHhz 80W Harpertown (1) 45nm 2 4MB 1.6 to 3GHhz 65W Harpertown (2) 45nm 8 12MB 1.6 to 3GHhz 80W Dunnington 65nm 4 to 32 12MB 1.6 to 3GHhz N/A