Conclusions
Hardware/software co-design architecture for two typical MIMO lattice decoding algorithms has been designed and implemented in this thesis. The closest lattice point searching procedure is partitioned into the FPGA-based hardware modules. And a MicroBlaze soft core is used for the channel matrix preprocessing and R/I decomposition. Three levels of parallel structures are designed in this co-design architecture to improve the decoding rate. The overheads involved in these parallel structures are also analyzed. The proposed architecture is prototyped on the Xilinx XUP Virtex-II Pro developing board with an XC2VP30 FPGA. The experimental results show that the AV and VB based decoders can reach up to 81.5 Mbps and 37.3 Mbps decoding rate respectively at 20 dB Eb/N0 for a 4×4 MIMO system with 16-QAM modulation, which are among the fastest MIMO decoders to the author’s knowledge. They are about 37 and 187 times faster than their respective implementations in a DSP processor. The BER performance of the experimental prototype matches with the software simulation results.
The implementation results show that our FPGA-based HW/SW co-design architecture is a promising solution to design efficient MIMO decoders to match with the high transmission rate in MIMO systems. This thesis research also provides author an excellent opportunity to learn the procedures involved in the HW/SW co-design and to get invaluable experiences on real issue designs.
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Vita
Cao Liang was born in 1979, in Sichuan, China. He received the B.S. degree in Electrical Engineering from University of Electronic Science and Technology of China in 2002. After the graduation, he worked in Sifang Information & Technology Co., Ltd as a software engineer for more than one year. In fall 2004, he began his graduate studies in the EE department at University of New Orleans.
His research is mainly focused on embeded computer systems for high performance computation and wireless communications.