Convolutional Decoding Methods and the Modified Feedback Decoding Algorithm
DMCconvolutional
3.2 Considerations for the Implementation of the VA
The functional block diagram of a Viterbi decoder is shown in Fig. 3.3. The decoder is composed of the following blocks |20]: branch metric computer (BMC), add-compare- select (ACS), storage survivor memory (SSM), and output decision (OD). The BMC block performs multiplication, the ACS block performs addition, m axim um or m inimum selection and path metric storage, the SSM block keeps track of the decisions made in the ACS block in a hypothesised digital representation and the OD block outputs the decoded data. In addition, the decoder is equipped with a synchronisation function [50] so that it can determine the beginning of each n-symbol block in the received sequence r.
ACS- l o o p
/
BMC ACS SSM OD
Figure 3.3 Simplified block diagram of a Vilcrbi decoder.
3.2.1 The BMC Block
Each time a new //-symbol block is received, the BMC block computes a new set of branch metrics, one for each branch of the trellis diagram. In most cases the BMC block is based on a look-up table containing the various symbol metrics. The resulting branch metrics form the inputs to the ACS block. For optimal VA performance in A W G N , the branch metric of a given transition is defined as the squared Euclidean distance between the received //-symbol block, and the //-symbol code block of that transition. That is, the branch metric , in Eq. (3-4) is given by
/ = ! /=!
(3-7)
where r, = (/'/‘^, /'/“^, . . . , /-/"^) is the received block at time f, v = (/-■/', , . . . , /'J/''’ ) is the code block of the transition from state S^ to state , and ( I < / < / / ) is the /th symbol metric of the transition from S ^ at time t to 5, at time / + l . By expanding Eq. (3-7) into
h u = £ ( ' ■ / " ) ' - 2 £ ( r / '> ■ v < ; > ) + £ ( v 5 ' > ) ^ (3-8)
/=! /=1 /=1
it is observed that the first term on the right of Eq. (3-8) is common to all branch metrics, and thus it can be discarded since it contributes equally to all branch metrics. In fact, the metrics can always be scaled by adding (or subtracting) some constant to all of them or by multiplying (or dividing) all of them by a positive constant.
In the case of antipodal signalling (BPSK) where the normalised code symbols are represented by -1 and -hi depending on whether the code symbol is a “0” or a “ 1”, respectively, only negation operations are required to compute the symbol metrics [47] (the last term in Eq. (3-8) is always 1 and so it can be neglected). Thus,
(/) _
,,(/) _
ji
- for = -hi
! < / < % (3-9)
for vjf = -1
Note that in order to retain the term max in Eq. (3-4) the sign of the results in Eq. (3-9) must be inverted. Otherwise the term max in Eq. (3-4) must be replaced by min. Note also that to be able to implement Eq. (3-7) exactly, an analogue realisation must be adopted. However, in practice the received sequence is usually quantised to eight levels before being fed into the decoder and thus, each symbol metric is represented by a 3-bit binary word.
For the BSC with a channel error rate of p < 1/2, Hamming distance is the preferred metric. In this case the per symbol metric is given by
\ < l < n (3-10)
which may be realised using an XOR circuit. The sign of the results in Eq. (3-10) is in the correct format required to retain the term max in Eq. (3-4).
3.2.2 The ACS Block
The ACS block takes the branch metrics computed by the BMC block and computes the path metrics at each node in the trellis. At each time instant, the survivor path for each state is selected, and the SSM block is updated accordingly. The operations performed by
the ACS block are better understood by breaking the trellis up into a num ber of identical modules as shown for the R = \/n case in Fig. 3.4a. Since the entire trellis is constructed from replicas of this “butterfly” module, the computational unit shown in Fig. 3.4b can be used recursively to realise the ACS block, and hence Eq. (3-4). Since the basic operations performed by this unit are addition, comparison, and m aximum or m inim um selection (and storage), the unit is referred to as the add-compare-select unit (ACSU). It should be noted that the A C SU in Fig. 3.4b might also be employed in high-rate punctured codes (see Section 2.3.6). 7'. ' lim e to S S M to a n o th er A C S U A C S - l o o p A dd A dd C o m p a re (a ) ( b )
Figure 3.4 (a) Basic trellis module for a R = 1//; convolutional code, (h) Block diagram of the ACSU used for the same code.
For slow Viterbi decoders a state-serial architecture [51] is adopted whete one AC SU (or a few) is time-shared. For high-speed Viterbi decoding a state-parallel architecture [52] is em ployed where 2 ^ “* A C S U ’s are working in parallel. Generally, the m axim um operating speed in a state-parallel implementation is limited by the propagation delay around \\\q ACS-loop. Therefore, the design of the ACSU is crucial in determining the key performance parameters of a Viterbi decoder, that is, speed, complexity, size and power consumption.
As seen from Eq. (3-4) unbounded growth of the path metrics is an inherent problem with the VA. To avoid path metric overflow and to reduce the required dynamic range in internal calculations, several methods for normalising the survivor metrics have been considered [53]. The complexity involved in the normalisation process depends on which design solution is adopted. One solution requires that at each time instant the smallest survivor metric be subtracted from all others, thus forcing the m inimum metric to remain at around zero. However, this solution requires extra circuitry for selecting the smallest
path metric, and hence it is not usually adopted in practice. Instead, the threshold technique is usually employed where a fixed threshold is subtracted from all path metrics when they all exceed a threshold value. The threshold technique may be realised by taking an average over all survivor metrics in each time instant and subtracting it from all path metrics when the average exceeds a threshold [13]. The threshold technique may be extended to selecting any arbitrary state and periodically monitoring its path metric. W hen the path metric at that state exceeds a threshold value, the amount of the difference is subtracted from all path metrics, and thus the path metric of the monitored state is forced to remain around the threshold. Finally, in digital realisations the extra computation required for metric normalisation may be easily avoided by using 2 ’s complement arithmetic to implement Eq. (3-4) [54].
3.2.3 The SSM Block
The SSM block is responsible for keeping track of the information bits associated with the survivor paths computed by the ACS block. The two fundamental design approaches for realising the SSM block are the register-exchange and traceback techniques. In both techniques each state in the trellis diagram is assigned a shift register. The number of symbols that a shift register must be capable of storing depends on the survivor depth W, which in practice is usually chosen to be about 5K .
In the register-exchange [20] technique, the information symbols associated with the survivor path for each state are stored directly and the registers in which these symbols are stored are interconnected in the same order as the ACSU’s. Each time a new «-symbol block is processed by the decoder, the contents of the registers are updated and exchanged depending on which paths survived the ACS comparisons. A new symbol is then added at one end of each shift register, and the oldest symbol in each shift register is delivered to the OD block. The major disadvantage of this technique is that the complete history of the survivor path for each state has to be updated at each time instant. In addition, the registers must be capable of sending and receiving strings of symbols to and from one of two different locations. At high speeds all the exchanging must take place simultaneously, resulting in very complex hardware realisation. Therefore, this technique is usually only suitable for relatively slow or small (up to about K = 5) decoders. However, from a functional point of view this technique is very simple and does not require any trace back to find the decoded bits. That is, at time t the information symbol
associated with the branch at time t - W is read directly as the oldest bit of the selected shift register. Fig. 3.5 shows the contents of the registers for the VA deeoding example in Fig. 3.2 assuming register-exchange realisation.
0 ( ) - - - - 0 0 0- - - 0 0 0 0 - 0 0 0 0 0- 0 0 0 0 0 0 7ZZZZZZL 0 1- - -
I
0 10—^ V / / / / / / Æ 01 I 1 I 0^ 0 I I0-- 01 1 10-> '///////}/ 0- - - - 0 0- - - 0I0-- 10 1 10- 0 0 0 0 0 2 K - \ 1 1 1 0 - - - 1 1 1! I l O - lregister bank register bank register bank register bank register bank register bank register bank
I = 0 1 = 2 / = 3 1 = 4 1 = 5 I = 6
Figure 3.5 Path memory eonlcnts for the Viterbi decoding example in Fig. 3.2 using the register-exchange approach.
The traceback technique [55] is more eommonly utilised and uses pointers to keep track of the survivor paths. That is, at eaeh time instant there is no need to store the information bits associated with the survivor path at each state, but instead only the results of the ACS comparisons are stored. The deeoder outputs information bits by selecting a shift register at time t and recalling the pointers in the reverse order in which they were stored. The information bits associated with the branch at time t - W are then output. At high speeds this technique enables decoding of several branches at eaeh trace-back. The pointers in the shift registers are updated in a first-in-first-out manner and are eontinuously overwritten. For the trellis diagram in Fig. 2.7, Table 3.1 represents the pointers assigned for the transitions from time t to time r -t-1. Based on this truth table, Fig. 3.6 shows the
Table 3.1 Time transition pointers for the trellis diagram in Fig. 2.10.
t + \ o ES3 3 " n n □ sta te E53 EH] □ 0 I N C N C N C N C 0 1 0 1 N C N C N C N C 0 I N C = no c o n n e c tio n
- - - - 0 0 - - - 0 0 0 - - 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 ::1 [> - - - - 0 0 - - - 0 0 0 ^ TZZZZZZZ?- - 0 0 0 I ÿrZZZZZZZZ-00011 Yf 'yyyyyyyyyA TZZZZZZZZ.0 0 0 - - - - 0 0 - - - 0 0 - - 0 0 1 1 -001 10 I K - I 1 - - - 0 0 1 1 - - 0 0 1 1 1 -00 110
register bank register bank register bank register bank register bank register bank register bank
t = 0 t = 2 t = 4 1 = 5 I = 6
Figure 3.6 Path memory contents for the Viterbi decoding example in Fig. 3.2 using the traceback approach.
contents of the legistets for the VA decoding example in Fig. 3.2 assuming traeebaek realisation.
3.2.4 The OD Block
Tiie OD block determines the decoder output and it also provides information to the decoder synchroniser. The implementation complexity of the OD block depends on which design solution is adopted. At a given time r the deeoder must output the information bits assoeiated with one of the branches at time t - W . Because at time t there are still 2^'^"'^ survivor paths to choose from, the deeoder can either select the one with the largest metric, or select one at random [20|. The first solution offers optim um coding performance and always results in the lowest probability of error but at the expense of increased complexity. In this ease the OD block is essentially a W T A netw ork^ [19]. For the second solution, although the realisation is simple, only moderate values of CG are usually achieved. However, as W is increased, a point is reached beyond which all paths through the trellis coincide and hence the difference in performance between the two approaches becomes negligible. In practice, computer simulations are usually used to determine the optim um combination of VF and decision technique.
2 The function of the WTA network is to select and identify the largest variable I'rom a specified set of M