Corrections to Radar Documentation and Programming

In previous analysis of the preprogrammed waveform was it discovered that the output from the LO-board mismatched the predescribed programming documentation [34, p.5]. Hence were the programming code reviewed. The review of code versus output, seen in relation to figure 6.2, discovered that profile pin (P0), were set correct with a total

modulation time of 50 ms between each new sweep. However were the DDS frequency step ∆f set to 200 Hz, matched to a total frequency sweep of 1 GHz. In contrast should the chirp rate instead have been matched to the bandwidth of the DDS output (BWDDS),

as the frequency sweep is automatically terminated at the stop frequency (E0, at DDS

output). When the stop frequency in contrast had been set correctly to 66.265 MHz matched to the DDS output, the chirp was supposedly terminated after the measured 132µs with the ∆t set to 8 ns. As previously measured were also the chirp bandwidth to wide according to the ESTI requirement, making the stop frequency appear at 77.132 GHz. Thus were it appropriate to change the DDS stop frequency, in addition to new matching of the chirp rate for a correct chirp sweep time. However was the measured chirp time not consistent with the new derived theory. According to new theory the

6.2. Corrections to Radar Documentation and Programming 111

measured chirp time should have been

∆f = 200 Hz (errorous) S0 = 65.292 M Hz and E0 = 66.265 M Hz Nsteps= BWDDS ∆f = 973kHz 200Hz = 4865 t0 = ∆t · Nstep= 38.92µs

From the sweep time estimate it seemed that the DDS feed a unfavorable chirp in to the PLL. Hence as the spectrograms in section 5.1.4 show did it seemed that the PLL were struggling to find some reference within the chirp and wiggling about with large variations in frequency until it finally got track of the hold frequency after 132µs. This indicated that the chirp time had to be at least set longer than 140mus. By looking at the design note [5, p.39], showing a simulated PLL lock time of 568µs to a 10kHz frequency step, it was decided that the minimum chirp time should be ≥ 1 ms to yield a more favorable condition for the PLL, to produce linear chirps.

If the previous modulation should have been used, to generate a modulation of 40 ms chirp and 10 ms hold time, it had to be set accordingly as

Nsteps=

t0

∆t = 40ms

8ns = 5e6 time steps

∆f =BWDDS Nsteps

= 973kHz 5e6

∆f = 0.195 Hz ≈ 0.23 Hz

Rounded to closest∆f which gives an integer RDW/FDW = 2

Newt0 due to rounding, choosing RDW/FDW=2

t0 = 33.8 ms

Additionalt0 due to rounding, choosing RDW/FDW=1

t0 = 66.8 ms

The derived relation show that the use of maximum time resolution(RSRR/FSRR=1), for long modulation periods would be difficult due to frequency word rounding and the fact that the setRDW()/setFDW()-function would only handle integer RDW/FDW. Hence had RSRR and FSRR to be increased if such modulations should be implemented in the further.

6.2.1. Corrected DDS Source Code Settings

From the above relations, section 6.1 and the DDS documentation [10], a general method were derived for correct DDS sweep settings, seen in relation to figure 6.2

First, insure that the modulation period controlled by microcontroller, match the total time of the desired waveform including both the chirp and eventual hold periods (profile pin). Set in the C-code as DDS_T ASK_DELAY and matching

ROT _SW IT CH_T ASK_DELAY as a decimal number that corresponds to number of ms. Hence the number 50 = 50ms modulation before new frequency sweep will be initiated.

Further derive the desired start and stop frequencies at DDS output in relation to W-band output (see section6.1.3)

E0 = fM M W(High) 1164 S0 = fM M W(low) 1164 Hence will the DDS chirp bandwidth be

BWDDS =E0− S0

The desired chirp sweep time will be defined by the DDS time step and number of steps t0 =∆t · Nstep

Thus will the desired chirp time yield the number of steps required Nstep =

t0

∆t

Finding the required DDS frequency step that overholds the time requirement ∆f =BWDDS

Nstep

The required RDW would then be given by equation 6.2 RDW =∆f

fsys

· 232

⇓ C − code

RDW =|RDWdecimal|HEX

To use this relation in the C-code the decimal RDW needs then further to be converted to HEX-decimal values, to set correct register values. This method would yield for both raising and falling chirps. The used DDS frequency word setting and timing are presented in appendix C.1.

6.2. Corrections to Radar Documentation and Programming 113

6.2.2. Additional Mircocontroller Source Code Corrections

After new DDS frequency words had been applied to the source code and instructions loaded to circuit, the waveform were analyzed with the spectrogram-method. However did these first tests yield no improvement to the waveform. The same problem with short nonlinear chirps appeared also after corrections to the DDS settings had been made. Several waveforms of different modulations where hence tested. However did the profile pin follow the desired programming, making the total waveform period consistent with programming. This led to a further investigation of the source code since it seemed that chirp were not initiated at all and that the visual chirp moreover could possibly be the frequency transition between large frequency gaps generated by the PLL with no reference within the gap.

After intensive testing of different programming approaches were it hence discovered that the used case-based structure of the source code main file laked a initialization of the RDW and FDW in each case switch position. By setting the RDW and FDW by the setRDW() and setFDW() methods within each case the new programming applied as it should. The new initialization of the case-based main file are shown in appendix C.1.1. The delivered code had hence initialized the sweep mode correctly but missed setting the ramp rate words at each position. With use of the mechanical switch had thus the previous ramp rate word been erased from µC memory and thus produced a 2-FSK modulation rather than a LFM. Since the DDS circuit was combined with a PLL, had the PLL produced a frequency transition with linear like properties. Seen with a standard spectrum analyzer had thus the transition produced enough power to be mistaken as the desired chirp. As the previous waveform analysis showed, had the transition contained anought linear characteristics to be mistaken for just a unfavorable chirp generation and hence produced a ambiguous waveform to real chirps, seen both in the spectrogram and the linearity test. The linear properties were in fact so ’good’ that transition had produced a synthetic beat frequency, but with high nonlinear effects present as described in chapter 5.2. Thus had had source of error been found and all confusion around the previous waveform performance had been caused by a simple programming error. However had the previously derived methods been very essential to identifying that there actually had been a real problem of waveform timing and verification of the validity of new applied code.

After reprogramming with the need initialization, the new waveforms seemed to be flawless compared to the previous transition. However did the initial tests confirm the transition hypothesis, when pure Up-chirp modulations were initiated and closely exam- ined. Figure 6.6 show the zoomed-in frequency transition between two 10ms up-chirp FMCW waveforms obtained with the spectrogram method, purified with the maximum power method and up-converted in MATLAB to W-band. The discovered transition showed great resemblance with the previously studied transition both in frequency devia- tion and time (120 µs). Hence fully confirming the hypothesis and also indicating the circuits typical sweep recovery time (tsr) to up-chirp waveforms.

0.46 0.48 0.5 0.52 0.54 0.56 76 76.2 76.4 76.6 76.8 77 Time [ms] Frequency [GHz]

Figure 6.6.: Circuit frequency transition between large frequency gaps, 10ms up-chirp waveform,

Upconverted to W-band