DDS Setup

To operate the DDS as described in section A.11 the desired frequency words needed to be set along with with the general operation register settings described in radar docu- mentation [34]. In aspect of pure frequency modulation the most important DDS settings are the single frequency and frequency sweep settings, in order to define appropriate modulation.

Single Frequency Setting:

The output frequency from the current DDS, was predefined by the frequency tun- ing word FTW, the presicion of the phase accumulator (232) and the DDS main clock (fsys = 500 M Hz).

fDDS =

F T W 232 · fsys

By rearranging the above expression the FTW could be set to a desired DDS output frequency. By this relation were the CW set to the desired CW frequencies and the start/stop frequencies of the DDS in frequency sweep mode

(FTW0 = S0(start), FTW1 = E0(stop)).

F T W = fDDS fsys

· 232

(6.1)

Frequency Sweep Setting:

Further more were the DDS programmed for different types of frequency sweep modes/ modulations. The AD9958 DDS allowed two general linear frequency modulations schemes, hence up-chirp modulation and triangular. The selection of modulation were enabled by setting appropriate register values. To operate the DDS as a LFM signal

6.1. Microcontroller Settings and Programming 107

source, two initial register positions needed to be set, CFR[23:22]=2 to enable frequency sweep and CFR[14]=1 to enable linear modulation. Additionally to assign the desired modulation of up-chirp or triangular mode the DDS had to be assigned a value to the NODWELL-register position, respectively high or low. The no-dwell-high yield that the frequency sweep are only performed one way, sweeping from a start frequency (S0)

to a stop frequency (E0) and further reseting the modulation to start over again at S0 at

next initiation of sweep start. On the other hand would no-dwell-low yield both use of frequency sweeps both up and down, shown in figure 6.2, 6.3 and 6.4.

Figure 6.2 is taken from the DDS datasheet [10] to show the setting of frequency word that would make out the chirp/waveform.

FR E Q U ENC Y LI N E AR S W E EP RDW RSRR FSRR Δf FDW TIME S0 E0 PROFILE PIN Δf Δt Δt BWDDS = E - S0 0 P0 or P1

Figure 6.2.: DDS frequency sweep tuning words

The above figure show that the profile pin in the desired channel (P0or P1), defines the

modulation period of the waveform until the next sweep will be initiated. Thus was it important to align the sweep rate between S0 and E0such that the sweep time were as

desired and thus corresponding to the time were profile pin were set high, since the next sweep did not occur until the profile pin was set high again. However in the case of no- dwell enabled (up-chirp), would profile pin set to zero, yield immediate start-up after E0

had been reached. Since the DDS had been overrided by the microcontroller, the profile pin timing had to be set appropriately through the source code (T ASK_DELAY ). In addition had also the sweep rate to be set appropriately to achieve the desired modula- tion in respect to frequency and time since the sweep would eventually stop after E0had

been reached. The frequency step of DDS ∆f , seen in figure 6.2, were depend of the defined raising delta word (RDW/FDW), the frequency word resolution of 32-bit (232) and the system clock.

∆f = RDW

232 · fsys (6.2)

Hence could RDW or FDW be obtained by rearranging the equation for a desired ∆f . Also seen from figure 6.2 did the time step ∆t have to be set, which together with the RDW/FDW defines the chirp rate of the sweep. Notably did the relation between ∆t and

∆t also define the chirp time, since the sweep finishes when the fDDS would reach the

value of the stop frequency, seen in figure 6.2 as E0. The time step was defined by the

raising/falling sweep ramp rate word (RSRR/FSRR) and the DDS syncronisation clock fsync= fsys/4 = 125M Hz.

∆t = 1 fsync

· RSSR (6.3)

Since it is desired for FMCW radars to yield good frequency linearity the time resolution was set to a minimum, by RSRR/FSRR = 1. Thus implying that more and smaller frequency steps were needed to uphold the desired chirp time. With RSRR and FSRR set to 1 the resulting minimum time step were 8 ns.

Up-chirp modulation:

FTW0

SINGLE-TONE MODE

LINEAR SWEEP MODE ENABLE (NO-DWELL BIT SET) FTW1 A A A B B B

f

OUT TIME P2 = 1 P2 = 0 P2 = 0 P2 = 1 P2 = 0 P2 = 1

Linear Sweep Mode (No-Dwell Enabled)

Figure 6.3.: DDS register setting, operating in up-chirp mode

Figure 6.3 show the basic operation of the DDS in no-dwell mode (up-chirp)[10], were A defines the start up of modulation (profile pin high). The point B is hence the point of modulation where the stop frequency have been reached (F T W 1 = E0), and the

modulation starts over again at next profile pin high. Triangular modulation:

Figure 6.4 show the scheme of the DDS operated as triangular modulation signal source. The point A still yield to the position were the up-sweep is initiated by the profile pin. However would the dwell now insure no start-up of down-sweep until pin have been disabled. Hence would the total time this pin were high make out the modula- tion period of chirp with hold until next modulation starts over sweep in another direction.

6.1. Microcontroller Settings and Programming 109

FTW0

SINGLE-TONE

MODE LINEAR SWEEP MODE

AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RDW<31:0> AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FDW<31:0>

P2 = 1 P2 = 0 P2 = 0 TIME FTW1 A B

f

OUT _{Linear Sweep Mode (No-Dwell Disabled)}

Figure 6.4.: DDS register setting, operating in pure triangular or hold mode

In document Realization of a DDS/PLL Signal Source for W-band Radar Applications: Automotive FMCW Radar (Page 120-123)