Chapter 3 Device Modelling
4.3 Correlation between Device Structure and Small-Signal Model
4.3 Correlation between Device Structure and Small-Signal
Model
The lumped elements in the equivalent circuit model are superimposed on the cross- section of a GaN HEMT device as shown in Figure 4.2.
Figure 4.2: Basic device structure and physical correlation of the parameters in the small-signal equivalent circuit for a GaN HEMT.
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Pad Capacitance: The capacitances Cpg and Cpd (not in Figure 4.2) are the capacitance between the contacting bond pads at the gate and drain terminals respectively. Extrinsic Resistances: The source-to-channel (Rs) and drain-to-channel (Rd) resistances are the accumulation of the resistance due to ohmic contacts, resistance between the metal electrodes and cap layer and also the bulk drift region resistance between the drain contact and the end of the channel. The gate resistance (Rg) is the gate-metal resistance due to the Schottky contact at the gate.
Extrinsic Inductances: The metallization of the gate, drain and source contacts of the device surface respectively give rise to the gate (Lg), drain (Ld) and source (Ls) inductances.
Intrinsic Capacitances: The gate-to-source capacitance (Cgs), also known as the input capacitance, depends on the gate-to-channel capacitance through the barrier layer at the gate side (Cgs1), the fringing capacitance between gate and source electrodes (Cgs2), and the parasitic capacitance between gate and source-terminated field plate (Cgsp). The total gate-to-source capacitance is as follows:
gsp gs
gs
gs C C C
C 1 2 (4.1)
The gate-to-drain capacitance (Cgd) depends on the gate-to-channel capacitance through the barrier layer at the drain side (Cgd1) and the fringing capacitance between gate and drain electrodes (Cgd2) and given by:
2 1 gd gd gd C C
C (4.2)
The capacitance Cgd provides a feedback path between the input and output of the device. Therefore, Cgd is also called the feedback capacitance. The drain-to-source capacitance (Cds1) is the geometric capacitance between the drain and source electrodes in the buffer layer as shown in Figure 4.2. The parasitic capacitance between drain and source-terminated field plate (Cdsp) also contributes to the total value of Cds which is given by:
dsp ds ds C C
C 1 (4.3)
Intrinsic Resistances: The origin of resistances Ri and Rgd is related to the resistances from the gate to source and drain respectively, because in a GaN HEMT, the quantum well of charge carriers is separated from the gate by an AlGaN cap layer. The Ri and
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Rgd are the intrinsic charging resistances associated with the finite time required by the capacitances Cgs and Cgd to setup and the time constants are expressed by RiCgs and RgdCgd respectively. These resistances are also known as access resistance and feedback resistance respectively.
Transconductance Delay: The transconductance delay (τ) is the time taken for gm to change in response to a change in gate voltage (VGS). In other words, it is the time taken by the channel charge to re-arrange itself when the gate voltage changes. Transconductance: When the FET is in the saturation region, the drain current IDS is primarily controlled by the gate voltage (VGS). The forward transconductance is determined by differentiating the saturated drain current with respect to the gate voltage for a constant drain voltage and given by.
DS GS DS m at constant V δV δI g (4.4)
It is a measure of how well the FET can control its drain current by changing the gate voltage. From (4.4), it can be seen that the transconductance, gm is the slope of the transfer curve or output characteristic curve of a FET and is a measure of its dc gain. It is always desired to be constant over a wide range of VGS since this implies better linearity. -4 -3 -2 -1 0 1 2 0.0 0.5 1.0 1.5 2.0 gm ( S ) VGS (V) (HEMT)
Cree CGH40025 (25 W GaN-on-SiC HEMT)
0 2 4 6 8 10
Freescale MRFE6VS25 (25 W Si LDMOS)
VGS (V) (LDMOS)
Figure 4.3: Transconductance (gm) of a 25 W GaN-on-SiC HEMT and a 25 W Si LDMOS as function of gate voltage (VGS).
Figure 4.3 shows the values of gm from measurement for a 25 W silicon LDMOS (Freescale MRFE6VS25) and a 25 W GaN-on-SiC HEMT (Cree CGH40025). The
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nearly constant and higher value of transconductance for the 25 W GaN HEMT over wider range of gate voltages than the 25 W Si LDMOS indicates higher linear output power and gain as would be expected from the material properties.
Output Conductance: Drain or output conductance (gds) describes how the drain current changes with respect to the change in drain-to-source voltage and given by following equation: DS DS ds δV δI g (4.5)
The drain to source resistance (Rds) is the reciprocal of output conductance (gds). It can be seen from Figure 4.4 that above a drain voltage of 5 V, the gds has fairly constant value of 0.015 S for the 25W GaN-on-SiC HEMT and 0.003 S for the 25 W Si LDMOS. This is the saturation region where the change in drain current in respect to drain voltage is insignificant.
0 1 2 3 4 5 6 7 8 9 10 0.0 0.1 0.2 0.3 0.4
Cree CGH40025 (25 W GaN-on-SiC HEMT) Freescale MRFE6VS25 (25 W Si LDMOS)
VDS (V) gds
(
S
)
Figure 4.4: Output conductance (gds) of a 25 W GaN-on-SiC HEMT and a 25 W Si LDMOS as
function of drain voltage (VDS).
The output conductance has a strong influence on the intrinsic voltage gain (Avi) of a transistor which is given by:
ds m ds m vi g R g g A (4.6)
The corresponding lower value of Rds in a device with high gds value results in lower voltage swing at the output and reduces the intrinsic voltage gain. Therefore, the lower value of gds in 25 W Si LDMOS would allow it to achieve higher intrinsic voltage gain than the 25 W GaN HEMT.
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In Figure 4.4, one can notice the ripple in the measured value of output conductance, which can be attributed to measurement errors. The primary sources of errors in I-V measurements are internal system noise, noise due to external electrostatic interference, insufficient settling time between test signal and measurement, resolution of the analog to digital converters, unwanted currents, poor connections and cables, and environmental conditions such as temperature, humidity and light. Although these errors cannot be eliminated completely, the measurement accuracy can be improved by using low noise connections and cables, allowing sufficient settling time, and implementing techniques such as shielding, guarding and proper grounding. The measurement accuracy can also be improved by taking the average of multiple measurements.
In the design process, yield analysis allows to consider these random variations from the nominal value of any parameter and to measure the effects on the performance specifications. The design can be then modified to minimize these effects through yield optimization [4.4].