Corresponding interrupt is handled using the N-N model 1 Corresponding interrupt is handled using the 1-N model.

4 Programmers’ Model 4.3 Distributor register descriptions

4.3.14 Non-secure Access Control Registers, GICD_NSACRn

The GICD_NSACR characteristics are:

Purpose The GICD_NSACRs enable Secure software to permit Non-secure software on a particular processor to create and manage Group 0 interrupts. They provide an access control for each implemented interrupt.

Usage constraints These registers can be implemented only if the GIC implements the Security Extensions. These registers are optional Secure registers. If not implemented, the corresponding address space is reserved.

Configurations These registers are present, optionally, in GICv2. The corresponding address space is reserved in GICv1.

The concept of selective enabling of Non-secure access to Group 0 interrupts applies to SGIs and SPIs.

GICD_NSACR0 is a banked register, with a copy for every processor that has a CPU interface and supports this feature.

Attributes See the register summary in Table 4-1 on page 4-75.

Figure 4-16 shows the GICD_NSACR bit assignments:

Figure 4-16 GICD_NSACR bit assignments

Table 4-20 shows the GICD_NSACR bit assignments:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field number, F NS_access fields

See the bit assignment table for more information about the properties of each NS_access[1:0] field.

Table 4-20 GICD_NSACR bit assignments

Bits Name Function

[2F+1:2F] NS_access, Field F If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI. Otherwise, the field is RW and configures the level of Non-secure access permitted when the interrupt is in Group 0. If the interrupt is in Group 1, this field is ignored. The possible values of the field are:

0b00 No Non-secure access is permitted to fields associated with the corresponding interrupt.

0b01 Non-secure write access is permitted to fields associated with the corresponding interrupt in the GICD_ISPENDRn registers. A Non-secure write access to

GICD_SGIR is permitted to generate a Group 0 SGI for the corresponding interrupt.

0b10 Adds Non-secure write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDRn registers. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVERn and GICD_ICACTIVERn registers. 0b11 Adds Non-secure read and write access permission to fields associated with the

4 Programmers’ Model

4.3 Distributor register descriptions

The GICD_NSACRn registers do not support PPI accesses, meaning that GICD_NSACR0 bits [31:16] are RAZ/WI.

For interrupt ID m, when DIV and MOD are the integer division and modulo operations: • the corresponding GICD_NSACR number, n, is given by n = m DIV 16

• the offset of the required GICD_NSACRn is (0xE00 + (4*n)).

Note

4 Programmers’ Model 4.3 Distributor register descriptions

4.3.15 Software Generated Interrupt Register, GICD_SGIR

The GICD_SGIR characteristics are:

Purpose Controls the generation of SGIs.

Usage constraints It is IMPLEMENTATIONDEFINED whether the GICD_SGIR has any effect when the forwarding of interrupts by Distributor is disabled by the GICD_CTLR settings. Configurations This register is available in all configurations of the GIC. If the GIC implements the

Security Extensions this register is Common.

The NSATT field, bit [15], is implemented only if the GIC implements the Security Extensions.

Attributes See the register summary in Table 4-1 on page 4-75.

Figure 4-17 shows the GICD_SGIR bit assignments.

Figure 4-17 GICD_SGIR bit assignments

Table 4-21 shows the GICD_SGIR bit assignments.

31 0 NSATTa Reserved 16 SGIINTID 14 Reserved 15 23 24 4 3 TargetListFilter 26 25 CPUTargetList

a Implemented only if the GIC implements the Security Extensions, reserved otherwise

Table 4-21 GICD_SGIR bit assignments

Bits Name Function

[31:26] - Reserved.

[25:24] TargetListFilter Determines how the distributor must process the requested SGI:

0b00 Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda_.

0b01 Forward the interrupt to all CPU interfaces except that of the processor that requested the interrupt.

0b10 Forward the interrupt only to the CPU interface of the processor that requested the interrupt.

0b11 Reserved.

[23:16] CPUTargetList When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the interrupt.

Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example

CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface.

If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any CPU interface.

4 Programmers’ Model

4.3 Distributor register descriptions

SGI generation when the GIC implements the Security Extensions

If the GIC implements the Security Extensions, whether an SGI is forwarded to a processor specified in the write to the GICD_SGIR depends on:

• whether the write to the GICD_SGIR is Group 0 (Secure) or Group 1 (Non-secure) • for a Secure write to the GICD_SGIR, the value of the GICD_SGIR.NSATT bit

• whether the specified SGI is configured as Group 0 (Secure) or Group 1 (Non-secure) on the targeted processor.

GICD_IGROUPR0 holds the security states of the SGIs, see the GICD_IGROUPRn description. In a

multiprocessor system, GICD_IGROUPR0 is banked for each connected processor, so the system configures the security of each SGI independently for each processor. A single write to the GICD_SGIR can target more than one processor. For each targeted processor, the Distributor determines whether to forward the SGI to the processor.

Table 4-22 shows the truth table for whether the Distributor forwards an SGI to a specified target CPU interface. [15] NSATT Implemented only if the GIC includes the Security Extensions.

Specifies the required security value of the SGI:

0 Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the