The corresponding interrupt is not pending on any processor.

1 • For PPIs and SGIs, the corresponding interrupt is pendinga _{on this} processor.

• For SPIs, the corresponding interrupt is pendinga _{on at least one} processor.

Writes For SPIs and PPIs: 0 Has no effect.

1 The effect depends on whether the interrupt is edge-triggered or level-sensitive:

Edge-triggered

Changes the status of the corresponding interrupt to: • pending if it was previously inactive

• active and pending if it was previously active. Has no effect if the interrupt is already pendinga_.

Level sensitive

If the corresponding interrupt is not pendinga_{, changes the status} of the corresponding interrupt to:

• pending if it was previously inactive

• active and pending if it was previously active. If the interrupt is already pendinga_:

• because of a write to the GICD_ISPENDR, the write has no effect

• because the corresponding interrupt signal is asserted, the write has no effect on the status of the interrupt, but the interrupt remains pendinga _{if the interrupt signal is} deasserted.

For more information see Control of the pending status of level-sensitive interrupts on page 4-100.

For SGIs, the write is ignored. SGIs have their own Set-Pending registers, see SGI Set-Pending Registers, GICD_SPENDSGIRn on page 4-117.

4 Programmers’ Model 4.3 Distributor register descriptions

4.3.8 Interrupt Clear-Pending Registers, GICD_ICPENDRn

The GICD_ICPENDR characteristics are:

Purpose The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC. Writing 1 to a Clear-pending bit clears the pending state of the corresponding peripheral interrupt. Reading a bit identifies whether the interrupt is pending.

Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements the Security Extensions:

• a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses

• if the GIC implements configuration lockdown, the system can lock down the Clear-pending bits for the lockable SPIs that are configured as Group 0, see

Configuration lockdown on page 4-82.

Clear-pending bits for SGIs are read-only and ignore writes.

Configurations These registers are available in all configurations of the GIC. If the GIC implements the Security Extensions these registers are Common.

The number of implemented GICD_ICPENDRs is (GICD_TYPER.ITLinesNumber+1). The implemented GICD_ICPENDRs number upwards from GICD_ICPENDR0. In a multiprocessor implementation, GICD_ICPENDR0 is banked for each connected processor. This register holds the Clear-pending bits for interrupts 0-31.

Attributes See the register summary in Table 4-1 on page 4-75.

Figure 4-9 shows the GICD_ICPENDR bit assignments.

Figure 4-9 GICD_ICPENDR bit assignments

Table 4-12 on page 4-100 shows the GICD_ICPENDR bit assignments.

Clear-pending bits

4 Programmers’ Model

4.3 Distributor register descriptions

For interrupt ID m, when DIV and MOD are the integer division and modulo operations: • the corresponding GICD_ICPENDR number, n, is given by n = m DIV 32 • the offset of the required GICD_ICPENDR is (0x280 + (4*n))

• the bit number of the required Set-pending bit in this register is m MOD 32.

Control of the pending status of level-sensitive interrupts

This subsection describes the status of an interrupt as includes pending if the interrupt status is one of: • pending

• active and pending.

For an edge-triggered interrupt, the includes pending status is latched on either a write to the GICD_ISPENDRn or the assertion of the interrupt signal to the GIC. However, for a level-sensitive interrupt, the includes pending status either:

• is latched on a write to the GICD_ISPENDRn

• follows the state of the interrupt signal to the GIC, without any latching.

This means that the operation of the Set-pending and Clear-pending registers is more complicated for level-sensitive interrupts. Figure 4-10 on page 4-101 shows the logic of the pending status of a level-sensitive interrupt. The logical output status_includes_pending is TRUE when the interrupt status includes pending, and FALSE otherwise.

Table 4-12 GICD_ICPENDR bit assignments

Bits Name Function

[31:0] Clear-pending bits

For each bit:

Reads 0 The corresponding interrupt is not pending on any processor.

1 • For SGIs and PPIs, the corresponding interrupt is pendinga _{on this} processor.

• For SPIs, the corresponding interrupt is pendinga _{on at least one} processor.

Writes For SPIs and PPIs: 0 Has no effect.

1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: Edge-triggered

Changes the status of the corresponding interrupt to: • inactive if it was previously pending

• active if it was previously active and pending. Has no effect if the interrupt is not pending. Level-sensitive

If the corresponding interrupt is pendinga _{only because of a write to}

GICD_ISPENDRn, the write changes the status of the interrupt to: • inactive if it was previously pending

• active if it was previously active and pending.

Otherwise the interrupt remains pending if the interrupt signal remains asserted, see Control of the pending status of level-sensitive interrupts

For SGIs, the write is ignored. SGIs have their own Clear-Pending registers, see SGI Clear-Pending Registers, GICD_CPENDSGIRn on page 4-115.

4 Programmers’ Model 4.3 Distributor register descriptions

Figure 4-10 Logic of the pending status of a level-sensitive interrupt

status_includes_pending Interrupt signal to GIC

GICD_ICPENDR

GICD_ISPENDR Write 1 b

b The register ignores a write of 0 Valid a _{read of}

GICC_IAR

a A read that acknowledges this interrupt Write 1 b

Bits corresponding to this interrupt

GICC_IAR: Interrupt Acknowledge Register GICD_ICPENDR: Interrupt Clear-Pending Register GICD_ISPENDR: Interrupt Set-Pending Register Read

Read

4 Programmers’ Model

4.3 Distributor register descriptions

4.3.9 Interrupt Set-Active Registers, GICD_ISACTIVERn

The GICD_ISACTIVER characteristics are:

Purpose The GICD_ISACTIVERs provide a Set-active bit for each interrupt that the GIC supports. Writing to a Set-active bit Activates the corresponding interrupt. These registers are used when preserving and restoring GIC state.

In GICv1, the GICD_ISACTIVERn registers are the RO Active Bit Registers, ICDABRn. Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI.

If the GIC implements the Security Extensions a register bit that corresponds to a Group 0 interrupt is RAZ to Non-secure accesses.

The bit reads as one if the status of the interrupt is active or active and pending. Read the

GICD_ISPENDRn or GICD_ICPENDRn to find the pending status of the interrupt. Configurations These registers are available in all configurations of the GIC. If the GIC implements the

Security Extensions these registers are Common.

The number of implemented GICD_ISACTIVERs is (GICD_TYPER.ITLinesNumber+1). The implemented GICD_ISACTIVERs number upwards from GICD_ISACTIVER0. In a multiprocessor implementation, GICD_ISACTIVER0 is banked for each connected processor. This register holds the Set-active bits for interrupts 0-31.

These registers are RO in GICv1 and RW in GICv2. Attributes See the register summary in Table 4-1 on page 4-75.

Figure 4-11 shows the GICD_ISACTIVER bit assignments.

Figure 4-11 GICD_ISACTIVER bit assignments

Table 4-13 shows the GICD_ISACTIVER bit assignments.

For interrupt ID m, when DIV and MOD are the integer division and modulo operations: • the corresponding GICD_ISACTIVERn number, n, is given by n = m DIV 32 • the offset of the required GICD_ISACTIVERn is (0x300 + (4*n))

• the bit number of the required Set-active bit in this register is m MOD 32.

31 0

Set-active bits

Table 4-13 GICD_ISACTIVER bit assignments

Bits Name Function

[31:0] Set-active bits For each bit: