System designers requested that the SSC help prevent a n u ndesired condi tion in the halt logic. When t he halt p i n is asserted on the m icro processor, it executes a speci a l trap to console code stored i n the ROM. A second assertion of t he CPU's h a l t p i n (typical l y generated when someone repeatedl y presses t he hal t button on the system front panel ) causes a second such trap, overwriting the poin ter needed to retu rn to program code u pon leaving consol e mode . Without t h is pointer, norma l operation o f t he machi ne cannot be resu med w i t hout booting. Obviously system designers wan ted to prevent this cond it ion .
Digital Technical journal
Figu re 1 SSC Photograph Showing Major Sections
Figure 2 SSC ROM Packing Connection Diagram
Digital Technical journal
No. 7 August 1988
The SSC prevents the second call by moni toring the addresses of all i nstruct ion reads and by i nter cepting a l l external hal t requests made to the C PU . During normal CPU operat ion , t he SSC passes an initial halt request to the m icroproces sor. The m icroprocessor i m mediately begins to execute from halt-protected space, w h ic h is a special address space programmed i n to the sse by t he user at boot t i me .
When the CPU reads t he first i nstruction from consol e code, t he sse detects this console code address and masks further halt requests. These 1 2 3
The System Support Chtp, a Multifu nction Chip for C VAX Systems
requests are masked as long as the m icroproces sor is executing ROM console code. The console code can then r u n u n i nterru pted by halts. During console code execution , the sse con t i nues to moni tor a l l i nstruction addresses. When an address outside halt -protected space is detected , the sse re-enables halt requests to the CPU .
Before decid i ng on the design descr ibed above , we considered impleme n ting a software-con tro l l ed bit that wou ld enable and d i sable halts. This scheme wou l d req u i re the software to set the bit upon entering hal t-protected space and to clear the bit upon re-entering norma l operation. AJthough apparently simpler, this scheme proved to be flawed because two condi t ions m ight occur that woul d prevent the user from halcing the sys tem : ( 1 ) the b i t coul d be accidenta l ly set by non boot code, or ( 2 ) a software error i n the boot code cou ld cause the m icroprocessor to start exe cuting nonsystem code.
With the plan we chose , control is automati cal ly returned to the user as soon as the software com pl etes execution of the assu mably bugfree halt- protected boot code. The system designer can , however, provide software control of the bah -enable fu nction by al ias i ng the boot ROM i nro rwo adjacent spaces, where on ly one copy is hal t protected . The software can then control halts by j u m p i ng between copies of the code. (This method is used on the MicroVAX I I a nd MicroYAX 3 5 00/3600 systems. )
UARTs
Although i t was clear from t he begi n n i ng that the SSC shou ld provide UARTs , the best choice for nu mber and design was not i m mediately clear. We had rwo choices at the time the chi p was defined :
• Dou ble-buffered DEC DLARTs ( DC-3 1 9) , which were i n wide use, although a few problems with this design had recently su rfaced
• Silo designs, which were becom i ng popu lar, though l arge in size
To conserve chip area, the sse team settled on a design very s i m i lar to the DEC DLART design, making a few i mprovemenrs i n response tO user requests. To keep from unduly complicating the design, we also decided to l imit t he number of UARTs to two ( the nu mber supported as console
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ports w i t h i n the VAX archirecture) .4 As a fu rther simplification , we l i m ited the n u m ber of baud rates ro eight power-of-two choices ( 3 00 tO :) 8 , 4 00 baud ) .
O u r most signi ficant improvement t O t he DLART design was the add i t ion of hardware control -P break-detect ion. Controi-P entered on a VAX console is i nterpreted as a halt request . Thus, the UART must pick ou t this special keystroke from the normal character stream and then signal the CPU to take appropriate action . Formerly, this function was performed by c u m bersome firmware . However, t h e SSC hardware conti nuously watches for this character and, when it senses control-P, automatica l ly signals the microprocessor.
The console code may configu re the SSC such that a break is defined as a controi-P or as 20 spaces ; the latter is a defi n i t ion sti l l used in some console appl ications. At one point, we had planned to use the chip t imebase tO define a break as a space lasting a fixed n u m ber of m i l l iseconds i nstead o f 20 spaces. However, users advised us that this new idea, a l t hough more e legant, wou ld make the UART more confusing to use .
Other i mprovements i nc lude better nOtifica tion of overru n and framing errors, and secure console support . Consol e secu r i ty is effected by a p i n . When grou nded , t he pin prevents a break from halting the CPU. This p i n is typica l ly con nected to a key switch on the computer's front pane l . Using the swi tch, the user can lock out console-induced hairs.
Further, t he SSC allows the CPU to direct ly access the UARTs, t ime-of-year c lock , a nd bus reset register by means of the VAX external pro cessor register protOcol . Using this protocol , the m icroprocessor can address system regi sters located outside t he m icroprocessor by register number rat her than by comp lete address . The sse u nderstands this protOcol and is capable of decod ing the register n umber and generating the desired response . Previously, VAX mod u l e designers using off-the-she lf UARTs had to imple men t a substa n t i a l amount of externa l logic tO decode the register addresses and enable the UARTs to respond to this protocol .
Finall y , t he UARTs su pport break transmit and loopback, and properly respond to VAX i n ter rupts . ln prod ucts containing the SSC, one UART is used as the system console; t he other is used for a u x i l iary fu nctions, such as remote diagnos t ics. or is d isabled .
Digital Technical journal