CONTROL
The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD
range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories:
When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed.
These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh.
When accessing the program memory block, the EEDATH:EEDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read.
The EEPROM data memory allows byte read and write.
An EEPROM byte write automatically erases the loca-tion and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.
Depending on the setting of the Flash Program Memory Self Write Enable bits WRT<1:0> of the Configuration Word 2, the device may or may not be able to write certain blocks of the program memory.
However, reads from the program memory are always allowed.
When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.
11.1 EEADRL and EEADRH Registers
The EEADRH:EEADRL register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory.
When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register.
11.1.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for EE memory accesses.
Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default.
Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.
The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine.
Interrupt flag bit EEIF of the PIR2 register is set when the write is complete. It must be cleared in the software.
Reading EECON2 will read all ‘0’s. The EECON2 reg-ister is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2.
11.2 Using the Data EEPROM
The data EEPROM is a high-endurance, byte address-able array that has been optimized for the storage of frequently changing information (e.g., program ables or other data that are updated often). When vari-ables in one section change frequently, while varivari-ables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.0 “Electri-cal Specifications”. If this is the case, then a refresh of the array must be performed. For this reason, vari-ables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.
11.2.1 READING THE DATA EEPROM MEMORY
To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 11-1: DATA EEPROM READ
11.2.2 WRITING TO THE DATA EEPROM MEMORY
To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
11.2.3 PROTECTION AGAINST SPURIOUS WRITE
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write.
The write initiate sequence and the WREN bit together help prevent an accidental write during:
• Brown-out
• Power Glitch
• Software Malfunction
11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT
Data memory can be code-protected by programming Note: Data EEPROM can be read regardless of
the setting of the CPD bit.
BANKSEL EEADRL ;
MOVLW DATA_EE_ADDR ;
MOVWF EEADRL ;Data Memory
;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read
MOVF EEDATL, W ;W = EEDATL
EXAMPLE 11-2: DATA EEPROM WRITE
FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
BANKSEL EEADRL ;
MOVLW DATA_EE_ADDR ;
MOVWF EEADRL ;Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATL ;Data Memory Value to write BCF EECON1, CFGS ;Deselect Configuration space BCF EECON1, EEPGD ;Point to DATA memory
BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs.
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write BSF INTCON, GIE ;Enable Interrupts
BCF EECON1, WREN ;Disable writes
BTFSC EECON1, WR ;Wait for write to complete
GOTO $-2 ;Done
Required Sequence
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF EECON1,RD
executed here INSTR(PC + 1)
executed here Forced NOP executed here
PC PC + 1 EEADRH,EEADRL PC+3 PC + 5
Flash ADDR
RD bit
EEDATH,EEDATL
PC + 3 PC + 4
INSTR (PC + 1)
INSTR(PC - 1)
executed here INSTR(PC + 3)
executed here INSTR(PC + 4) executed here Flash Data
EEDATH EEDATL Register
EERHLT
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)
11.3 Flash Program Memory Overview
It is important to understand the Flash program mem-ory structure for erase and programming operations.
Flash Program memory is arranged in rows. A row con-sists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.
Flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0>
of Configuration Word 2.
After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the EEDATH:EEDATL register pair.
The number of data write latches is not equivalent to the number of row locations. During programming, user software will need to fill the set of write latches and ini-tiate a programming operation multiple times in order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times.
The size of a program memory row and the number of program memory write latches may vary by device.
See Table 11-1 for details.
11.3.1 READING THE FLASH PROGRAM MEMORY
To read a program memory location, the user must:
1. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD control bit of the EECON1 register.
4. Then, set control bit RD of the EECON1 register.
Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle, in the EEDATH:EEDATL register pair; therefore, it can be read as two bytes in the following instructions.
EEDATH:EEDATL register pair will hold this value until another read or until it is written to by the user.
Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase.
TABLE 11-1: FLASH MEMORY
ORGANIZATION BY DEVICE Device Erase Block
(Row) Size
Number of Write Latches
PIC16(L)F1847 32 words 32
Note 1: EEADRL<4:0> = 00000
Note 1: The two instructions following a program memory read are required to be NOPs.
This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set.
2: Flash program memory can be read regardless of the setting of the CP bit.
EXAMPLE 11-3: FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL ; Select Bank for EEPROM registers
MOVLW PROG_ADDR_LO ;
MOVWF EEADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWL EEADRH ; Store MSB of address
BCF EECON1,CFGS ; Do not select Configuration Space BSF EECON1,EEPGD ; Select Program Memory
BCF INTCON,GIE ; Disable interrupts
BSF EECON1,RD ; Initiate read
NOP ; Executed (Figure 11-1)
NOP ; Ignored (Figure 11-1)
BSF INTCON,GIE ; Restore interrupts
MOVF EEDATL,W ; Get LSB of word
MOVWF PROG_DATA_LO ; Store in user location
MOVF EEDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location
11.3.2 ERASING FLASH PROGRAM MEMORY
While executing code, program memory can only be erased by rows. To erase a row:
1. Load the EEADRH:EEADRL register pair with the address of new row to be erased.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD, FREE and WREN bits of the EECON1 register.
4. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence).
5. Set control bit WR of the EECON1 register to begin the erase operation.
6. Poll the FREE bit in the EECON1 register to determine when the row erase has completed.
See Example 11-4.
After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
11.3.3 WRITING TO FLASH PROGRAM MEMORY
Program memory is programmed using the following steps:
1. Load the starting address of the word(s) to be programmed.
2. Load the write latches with data.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Pro-gram memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 11-2 (block writes to program memory with 32
The following steps should be completed to load the write latches and program a block of program memory.
These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. This unlock sequence should not be interrupted.
1. Set the EEPGD and WREN bits of the EECON1 register.
2. Clear the CFGS bit of the EECON1 register.
3. Set the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory.
4. Load the EEADRH:EEADRL register pair with the address of the location to be written.
5. Load the EEDATH:EEDATL register pair with the program memory data to be written.
6. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The write latch is now loaded.
7. Increment the EEADRH:EEADRL register pair to point to the next location.
8. Repeat steps 5 through 7 until all but the last write latch has been loaded.
9. Clear the LWLO bit of the EECON1 register.
When the LWLO bit of the EECON1 register is
‘0’, the write sequence will initiate the write to Flash program memory.
10. Load the EEDATH:EEDATL register pair with the program memory data to be written.
11. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The entire latch block is now written to Flash program memory.
It is not necessary to load the entire write latch block with user program data. However, the entire write latch block will be written to program memory.
An example of the complete write sequence for eight
After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will
continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
14 14 14 14
Program Memory Buffer Register
EEADRL<4:0> = 00000
Buffer Register EEADRL<4:0> = 00001
Buffer Register EEADRL<4:0> = 00010
Buffer Register EEADRL<4:0> = 11111
EEDATA EEDATH
7 5 0 7 0
6 8
First word of block to be written
Last word of block to be written
EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY
-; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF EEADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF EEADRH
BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,FREE ; Specify an erase operation
BSF EECON1,WREN ; Enable writes
MOVLW 55h ; Start of required sequence to initiate erase
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit to begin erase
NOP ; Any instructions here are ignored as processor
; halts to begin erase sequence
NOP ; Processor will stop here and wait for erase complete.
; after erase processor continues with 3rd instruction
BCF EECON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts
Required Sequence
EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
;
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL EEADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF EEADRH ;
MOVF ADDRL,W ;
MOVWF EEADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space
BSF EECON1,WREN ; Enable writes
BSF EECON1,LWLO ; Only Load Write Latches LOOP
MOVIW FSR0++ ; Load first data byte into lower
MOVWF EEDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF EEDATH ;
MOVF EEADRL,W ; Check if lower bits of address are '000'
XORLW 0x07 ; Check if we're on the last of 8 addresses
ANDLW 0x07 ;
BTFSC STATUS,Z ; Exit if last of eight words,
GOTO START_WRITE ;
MOVLW 55h ; Start of required write sequence:
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit to begin write
NOP ; Any instructions here are ignored as processor
; halts to begin write sequence
NOP ; Processor will stop here and wait for write to complete.
; After write processor continues with 3rd instruction.
INCF EEADRL,F ; Still loading latches Increment address
GOTO LOOP ; Write next latches
START_WRITE
BCF EECON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 55h ; Start of required write sequence:
MOVWF EECON2 ; Write 55h
Required Sequencee
11.4 Modifying Flash Program Memory
When modifying existing data in a program memory row, and data within that row must be preserved, it must
When modifying existing data in a program memory row, and data within that row must be preserved, it must