• •
11100 = Reserved. No channel connected.
11101 = Temperature Indicator 11110 = DAC output(1)
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2) bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information.
REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — ADNREF ADPREF<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded.
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2
001 = FOSC/8 010 = FOSC/32
011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4
101 = FOSC/16 110 = FOSC/64
111 = FRC (clock supplied from a dedicated RC oscillator) bit 3 Unimplemented: Read as ‘0’
bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit 0 = VREF- is connected to VSS
1 = VREF- is connected to external VREF- pin(1)
bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to VDD
01 = Reserved
10 = VREF+ is connected to external VREF+ pin(1)
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section 30.0 “Electrical Specifications” for details.
REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result
REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use.
REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result
REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result
16.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4. The maximum recommended impedance for analog sources is 10 k. As the
source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 16-1: ACQUISITION TIME EXAMPLE
TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
Note: Where n = number of bits of the ADC.
TA C Q = 2µs+1.12µs+50°C- 25°C0.05µs/°C = 4.42µs
FIGURE 16-4: ANALOG INPUT MODEL
FIGURE 16-5: ADC TRANSFER FUNCTION
CPIN
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS
Note 1: Refer to Section 33.0 “Electrical Specifications”. RSS = Resistance of Sampling Switch
Input
TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ADCON0 — CHS<4:0> GO/DONE ADON 145
ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 146
ADRESH A/D Result Register High 147, 148
ADRESL A/D Result Register Low 147, 148
ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 128
CCP4CON — — DC4B<1:0> CCPxM<3:0> 228
INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 89
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 90
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 94
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 136
DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 157
DACCON1 — — — DACR<4:0> 157
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
NOTES:
17.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a reference voltage to the following:
• Comparator positive input
• ADC input channel
• DACOUT pin
The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register.
17.1 Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
The DAC output voltage is determined by the following equations:
EQUATION 17-1: DAC OUTPUT VOLTAGE
17.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value.
The value of the individual resistors within the ladder can be found in Section 30.0 “Electrical Specifications”.
17.3 Low Power Voltage State
In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected.
Either the positive voltage source, (VSRC+), or the negative voltage source, (VSRC-) can be disabled.
The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source.
17.3.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE
The DAC output voltage can be set to VSRC+ with the least amount of power consumption by performing the following:
• Clearing the DACEN bit in the DACCON0 register.
• Setting the DACLPS bit in the DACCON0 register.
• Configuring the DACPSS bits to the proper positive source.
• Configuring the DACR<4:0> bits to ‘11111’ in the DACCON1 register.
This is also the method used to output the voltage level from the FVR to an output pin. See Section 17.4 “DAC Voltage Reference Output” for more information.
Reference Figure 17-1 for output clamping examples.
17.3.2 OUTPUT CLAMPED TO NEGATIVE VOLTAGE SOURCE
The DAC output voltage can be set to VSRC- with the least amount of power consumption by performing the following:
• Clearing the DACEN bit in the DACCON0 register.
• Clearing the DACLPS bit in the DACCON0 register.
• Configuring the DACNSS bits to the proper negative source.
• Configuring the DACR<4:0> bits to ‘00000’ in the DACCON1 register.
This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC module.
Reference Figure 17-1 for output clamping examples.
VOUT VSOURCE+–VSOURCE- DACR<4:0>
FIGURE 17-1: OUTPUT VOLTAGE CLAMPING EXAMPLES
R
R R
DAC Voltage Ladder (see Figure 17-2) VSRC+
DACEN = 0 DACLPS = 1
DACR<4:0> = 11111
VSRC
-R
R R
DAC Voltage Ladder (see Figure 17-2) VSRC+
DACEN = 0 DACLPS = 0
DACR<4:0> = 00000 VSRC
-Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source
17.4 DAC Voltage Reference Output
The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘1’. Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and
digital input threshold detector functions of that pin.
Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘0’.
Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure 17-3 shows an example buffering technique.
FIGURE 17-2: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
32-to-1 MUX
DACR<4:0>
R
VREF -DACNSS
R R R
R
R R
32 DAC
DACOUT 5
(To Comparator and ADC Modules)
DACOE VDD
VREF+
DACPSS<1:0> 2 DACEN
Steps
Digital-to-Analog Converter (DAC)
FVR BUFFER2
R
VSRC -VSRC+
VSS DACLPS
FIGURE 17-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
17.5 Operation During Sleep
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
17.6 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the DACOUT pin.
• The DACR<4:0> range select bits are cleared.
DACOUT + Buffered DAC Output
– DAC
Module
Voltage Reference
Output Impedance
R PIC® MCU
REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled
bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit
1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’
bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD
01 = VREF+
10 = FVR Buffer2 output 11 = Reserved, do not use bit 1 Unimplemented: Read as ‘0’
bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF
-0 = VSS
REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 136
DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 157
DACCON1 — — — DACR<4:0> 157
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused with the DAC module.