A task force was created in the ATLAS Collaboration in fall 2018, looking at the risks in a serial power chain. I participated as expert for the PSPP. This task force looked also at the other elements of the serial power chain and was lead by D. Bortoletto.
Further improvements of the front-end chip are being made, which include more safety features including over-voltage protection and under-shunt protection, preventing tran- sients by noisy modules. These features are added as response to observations made in system tests. There, the protection was done by the PSPP as described in section 6.2. The improvements in the front-end chip adopt in part the protection features of the PSPP. With the updates, the risk of a failing regulator to affect the entire module and chain (i.e. fe), is seen as very low. Also, the risk of open connectors and cooling failures
is deemed to be low as well.
The added complexity and risk with a PSPP has been estimated to be more of a disadvantage than the benefits from the flexibility in operation with a bypass. In spring 2019, the ITk Pixel collaboration decided therefore on a new baseline without the PSPP. The independent monitoring is still considered as an important feature. A PSPP without the bypass would add the same complications as with a bypass. Therefore, it was decided to use the DCS controller chip as a monitoring chip for the entire SP chain.
Chapter 8
Conclusion
The upgrade of the ATLAS ITk detector includes many challenges. The projected ra- diation dose will exceed everything so far observed. Research and development are con- cluding. The production of the detector is scheduled to be finished in 2026.
In this thesis, a control and monitoring chip for the new DCS of the ATLAS ITk Pixel detector was developed. This pixel serial powering & protection (PSPP) chip monitors voltage and temperature of the detector modules in a serial powered chain. Only four additional lines are required for power and communication of up to 16 PSPPs in a serial power chain. This allows operating PSPP independently of the pixel detector modules. A bypass transistor can switch individual modules in the chain with a current of up to 8 A while having a power loss smaller than 400 mW. The PSPP is working up to 800 Mrad of total ionizing dose (TID).
As M. F. Newcomer stated in response to irradiation results presented in this work [117]: “It actually seems quite amazing to use a process that allows stable operation up to 800 Mrad. Standard CMOS processes were only good to about 30 krad in the mid 90’s.”
8.1 Status and summary
The PSPP prototype chips developed in this work proved the concept of a detector control system for a serial power chain. A serial control bus (SCB) was enhanced to work reliably with AC coupled single-ended lines. Logic for the master of the SCB was implemented in an FPGA and the PARC test chip was used as a physical layer for the DCS controller. Two test chips (PARC and PATT) included a test logic which allowed to measure the single event upset (SEU) cross-section. The cross-section for a simple register was found to be 4.06 ± 0.08 × 10−14cm2. The data for the triplicated register
was not sufficient to make a precise statement. Theoretically, the cross-section for the triple modular redundancy (TMR) register could be up to 10 orders smaller than for a simple register. From the test beam data, the cross-section for the triplicated register is smaller than <1.7 × 10−17cm2.
The PSPPv3 was used in a system test for verifying the operation of a serial power chain. The integration of the PSPPv3 was straight-forward and it could be operated very reliably. During the commissioning and debugging of the system test, the PSPPv3 proved to be very useful. The monitoring values helped to identify problems in the
Chapter 8 Conclusion Development of a DCS Chip
modules. Further, the integrated automatic bypass activation protected the modules in case of over-voltage from damages. The results presented here were made with a serial power chain of seven quad modules. A larger structure with multiple chains is in the commissioning phase, where the PSPPv3 is included and already working.
The PSPPv4 is an updated version and was designed with radiation hard elements. It can bypass a current of 8 A without active cooling. The chip remains functional at 800 Mrad and includes protection against SEU. The PSPPv4 chip was tested in the climate chamber for more than 1 month at temperatures from (0 to 60)◦C. The same
chip is still in the climate chamber at a constant 85 % relative humidity and 60◦C. At
the time of this writing, it was operational and working for three weeks under these conditions.
Besides the development and verification of the PSPP chip, the concept and reliability of the detector control system for the serial power in the ITk Pixel detector were analyzed as part of this thesis. The PSPP chip adds complexity to the serial power chain and introduces additional risks. These have been addressed to be minimized. It becomes especially beneficial to the system when a single front-end chip can fail in a way that affects the entire chain. The commissioning, debugging and operation of the detector benefit from an independent monitoring path, as it allows to better investigate failures. Furthermore, the bypass adds the possibility to control single modules in the serial power chain.