DEPFET with non-linear amplification

The basic principle of a DEPleted Field Effect Transistor, abbreviated DEPFET, has been proposed in 1987 [38] and is illustrated in figure 4.4. The fully depleted high-resistivity n-type wafer is acting as the sensitive area. Depletion is achieved through sidewards depletion by reverse biasing the diode given by the p-doped back contact and the n-doped bulk.

On top of the substrate, a P-type field effect transistor (FET) is used as the first amplifier stage. A deep n+doping below the FET creates a potential minimum for electrons. Signal electrons created in the bulk drift towards the minimum and increase the conductivity in the channel by inducing mirror charges. Since the electrons in the minimum have an effect on the transistor current like the gate voltage on a typical FET, it is called internal gate.

Figure 4.4: 3D illustration of a DEPFET. The deep n doping is a potential minimum for signal elec- trons. The second n-doped area, the clear contact, is shielded from the bulk by an addi- tional p doping.

The change in current through the transistor dIdsis related to the signal charge dQsi gin the inter- nal gate and defines the internal gate amplification gq. According to the analytical model developed

1

4.1 The sensor in [38], it can be calculated to gq=dIds dQ = √ 2µpIds W L3_Cox (4.1)

where µpis the mobility of the holes in the PMOS channel and W and L are the dimensions of the channel. It is evident that the internal amplification can be improved by increasing the drain current and, more strongly, by shrinking the gate length and width. Typical values for a DEPFET are on the order of 300 to 500 pA per electron.

The charge in the internal gate can be removed by applying a voltage pulse to the n+doped clear contact and a second MOS gate called clear gate. The clear contact is shielded from the sensitive area by a deep p implantation, in order to prevent signal electrons created in the bulk from drifting towards the clear contact rather than the internal gate. The internal gate, the clear and the clear gate form an n-channel transistor allowing the signal charges to be extracted from the internal gate.

For noise calculations, the capacitance of the internal gate is needed, however, direct measure- ment is not possible. The effective capacitance of the internal gate can be defined geometrically:

Ce f f = W L

γ Cox = CG

f (4.2)

where f is a parameter describing the influence of the internal gate relative to an influence of the gate itself. It approaches unity when the internal gate is very close to the channel and is smaller for larger distances. An indirect measurement of the effective capacitance becomes available when we refer the effect of a signal charge qsi g in the internal gate to a voltage ∆Vg applied to the external gate with the same effect. This results in the definition

Ce f f = qsi g

∆Vg (4.3)

and has been measured to 40 f F [39].

With this definition, the equivalent noise charge for a DEPFET can be calculated by ENC2= a′ A₁1 τC 2 e f f + 2πa ′ fA2C2e f f + bA3τ (4.4)

with the following constants for the individual noise spectral densities a′= 4 3 kBT gm (4.5a) a′ f = KF W LC2 oxgm (4.5b) b= 2Il eake (4.5c)

for thermal noise, 1/f noise and shot noise, respectively. The coefficients A1, A2and A3are defined by the shape of the filter’s weighting function with the shaping time constant τ, which needs to be optimized according to the specific application case. It is evident that through the buried low- capacitance internal gate a low noise can be achieved.

The parameters a and af in equation 4.4 have been experimentally determined for DEPFETs in [39] with a drain current of 100 µA at 25○C as a= 1.53 × 10−16V2Hz−1and af = 4.5 × 10−12V2. The capacitance of the internal gate has been estimated in [34] as Cin = 60 fF. The parameter b for the

Figure 4.5: The equivalent noise charge for the DEPFET readout system (parameters given in the text) shows a minimum at a shaping time of about 800 ns for the chosen conditions.

parallel white noise can be estimated from the leakage current as b= 2Il eake. The leakage current should be below 100 pA cm−2at room temperature, resulting in b≈ 1.5 × 10−30A2s for a DSSC-sized pixel.

The resulting ENC depending on the trapezoidal shaping time is plotted in figure 4.5. A mini- mum noise of about 10 e-is reachable with the DEPFET. Note that the noise numbers given here only include the DEPFET noise and no noise contributions from any readout circuit element. For shaping times larger than 800 ns, the leakage current contribution rises further and dominates. For the foreseen operation at 4.5 MHz, a DEPFET noise of 30 e-can be estimated. It should be noted that the plot is valid for room temperature only, as leakage is strongly depending on temperature as in Il eak ∝ T3/2e

−EG

kB T_{. With lower leakage devices and longer shaping times, lower noise values}

have been realized with DEPFETs.

It is worthwile to note that reading the DEPFET is non-destructive, i.e. the charge collected in the internal gate is not altered. Measurements can thus be repeated for lower noise or charge can be stored in the internal gate, limited only by leakage current in the sensor volume which can be reduced by lower temperature. Repetitive measurements require alternating measurements of the baseline current and the current with signal charge. This has been demonstrated in [40] by using two adjacent DEPFET structures, between which the signal charge can be moved back and forth.

The DSSC-type DEPFET [42] uses a slightly modified pixel structure, depicted in figure 4.6. Here, the internal gate is split in several regions underneath a large-area source. The potential minimum for electrons is still located directly below the FET channel. Small signal charges are still accumu- lated below the channel, while large charges are distributed between the regions below the channel and the source. Only the parts below the channel have an influence on the FET current.

The non-linear characteristic of the device (figure 4.6 right) shows a linear part up to 30 keV to 40 keV. Here, additional charges start to fill the first overflow region below the source. The other overflow regions are filled at 600 keV and 2.5 MeV, respectively. The typical gqof a DSSC-type DEPFET is 500 pA/el to 600 pA/el for small signal charges.

4.1 The sensor

Figure 4.6: Left: Structure and potential in the non-linear DEPFET. Right: Simulated non-linear characteristic of the DSSC-type DEPFET [41].

Figure 4.7: Simplified layout of a DEPFET pixel. The hexagonal structure creates a more homoge- neous drift field compared to a rectangular pixel.

DEPFET itself is located in the center of the pixel (see figure 4.7). Charge electrons created in the sensor bulk are drifting to the pixel centers due to the static bias applied to the drift rings. The hexagonal pixel generates a more homogeneous drift area than square pixels, effectively reducing charge collection times. The DEPFET pixels have slightly larger pitch than the ASIC pixels, as the inevitable gaps between the ASICs are covered by sensor pixels as well. A redistribution layer from sensor pixels to ASIC bump bond landing pads is used on the sensor.

A sensor-internal charge injection possibility [43] has been studied in the scope of the DSSC project. Usually, the inner substrate contact, located between the two drift rings inside the pixel, is at a higher potential than the DEPFET source, effectively removing electrons generated at the device surface. By lowering the bias voltage electrons can be injected, which can spill over and reach the internal gate. This charge injection is planned to be used for system testing and calibration.