8.4 Periphery, ADC and front-end tests
The global voltage DAC is checked in P1 - the DAC is used further on to generate the stimulus for the ADC in the ADC4 test and to generate the reset voltage for the MSDD front-end checked in FE4. Since the DAC is binary scaled (with the exception of the LSB current sources), it is sufficient to measure only a few points of the characteristic in order to check every branch. Using a GPIB- controlled multimeter, the measurement could be fully automated. In the evaluation of the data, the overall offset and slope of the output characteristic are checked as well as the monotonicity, where the DNL of± 4 LSB has to be considered. No programmable ASIC has failed this test.
ADC1 is a simple check of the possiblity to set the start values for the gray code counters. Here, the timestamps are latched directly after the start of the ramp phase through the external latch functionality. Every single bit is checked by two patterns (0b10101010 and 0b01010101). No problems have been found here.
RAMP Latch 36 Memory input 37 38 Start of counter ∆t1 ∆t2 ∆t1< ∆t2
from ext. device
Figure 8.4: In the ADC2 test, an external latch signal is applied to all pixel ADCs with a frequency slightly slower than the repetition rate of the RAMP signal (top), thus increasing the latched value over time (bottom).
The digital domain of the ADCs is assessed by trying to latch every timestamp transmitted differ- entially from the counters and received in every pixel. An external high-accuracy Arbitrary Func- tion Generator (Tektronix AFG3252) synchronized with the test system is used to generate the pre- cise latch signals supplied to the ASIC. In order to minimize the time needed for this test, every
value should be latched in just one burst. The 800 storage cells in each pixel offer the possiblity of storing every one of the 256 bins three times. The latch signals are therefore generated with a slightly lower frequency than the ASIC cycle frequency of 4.5 MHz corresponding to a cycle length of 221.54 ns, so the latch signal is delayed from cycle to cycle by one third of the counter clock pe- riod of 719 ps with respect to the start of the counter. An illustration of the timing of the control signals and a sample measurement without missing codes is shown in figure 8.4. This measurement allows an easy and very fast assessment of the digital part of all 4096 pixel ADCs in parallel in just one burst.
While the tests on wafer level show a peak at a relatively large number of errors (figure 8.5), the same test run on ASICs flipped to sensors or interposers shows several orders of magnitudes lower error counts. Again, the test on wafer level is not suited for a characterization of the ADCs, but can be used to sort out ASICs with extensive problems of timestamp distribution. A limit slightly higher than the peak distribution at 50000 errors has been set.
Figure 8.5: The histogram of the missing timestamps per ASIC shows a peak at≈ 30000. These are typically randomly distributed throughout the pixel matrix.
The analog part of the ADC is tested in the ADC3 (Pixel Delay) and ADC4 (IRamp) tests. The sensor readout front-ends are tested in the FE1-4 tests. All these tests have been susceptible with regard to the quality of the needle connection to the balls. The main concern is the connection of the power supply needles and their corresponding sense needles. Two detrimental situations may appear while contacting with needles: High series resistance on the force or ground nets, and high resistivity or even open connection on the sense nets.
Series resistances are compensated by sensing the ASIC supply voltage at the ASIC level. In case of a high resistance over the needle-bump connection, the regulator increases its output voltage to generate the desired voltage at the sense point. This requires, however, a reasonable contact on the (single) sense needle. If both force and sense pins are poorly connected, the ASIC will suffer from a reduced supply voltage.
8.4 Periphery, ADC and front-end tests
Moreover, simulations have shown that the used LDOs may cause a high voltage, up to the reg- ulator input voltage, on the force lines in case of an open force sense connection. This has been resolved by adding 10 Ω between force and sense (and between ground and the respective sense) on the probecard, which ensures that no excess voltage is present at the ASIC input at any time. The fail-safe resistors do not prohibit sensing the supply voltage at ASIC level, which works well if a low-resistivity contact through the needle is established.
ADC3 tests the 70 ps delay steps of the ADC conversion, setting high requirements on the stabil- ity of the system. However, this measurement provided mostly inconsistent and not reproducible results. It is assumed to be strongly depending on contact quality, but also on temperature stability of the ASIC under test, which could not be realized easily in the given environment. ADC3 has therefore been excluded from further evaluation.
In the last ADC test, several voltages are applied to the ADCs from the previously tested voltage DAC in the periphery. The voltages are buffered by the in-pixel filter amplifier, allowing to test all ADCs in parallel without loading the monitor bus, and digitized for several ramp currents. The ramp current DAC is binary scaled, so the test only checks that every branch of the DAC is properly working. The control bit for current halving for 9 bit ADC operation is also tested. Reticles with more than 5 errors (0.1 % of the pixels) in this test have been sorted out, with only very few ASICs having failed this test.
Finally, the front-end tests aim to check the functionality of all building blocks for sensor readout. These are the current DAC for the sensor bias current subtraction, the flip capacitor filter, the pixel injection and the MSDD front-end branch. A threshold for KGD selection has been set individually for each test based on the results of the evaluation, such that ASICs with increased numbers of erroneous pixels are excluded, while providing enough ASICs for the precursor productions.
The bias subtraction DAC is checked by applying all available bias currents from the in-pixel injection circuit. For each setting, the DAC is sweeped while recording the Vholdvoltage for the current fine-tuning branch. Non-working branches of the DAC can be found by analyzing the behaviour of Vhold, as the variable branch accounts for 2.5 coarse DAC settings. Most ASICs proved to be working, so a threshold of 5 errors per ASIC has been set for KGDs.
The filter and the pixel injection, simulating a signal current from the DEPFET, are checked in FE2. A linear system response within the design parameters is expected here, checked by the offset (below 100 ADU) and slope (2± 0.5 ADU/injection code) of a linear fit for each pixel. Any irregu- larity is registered as an error here, with up to 100 errors (2.5 % of pixels) allowed. Optimizations of this test are possible by also checking the linearity figures (DNL, INL) of the resulting characteristic. Similarly, the filter gain settings, i.e. the four binary scaled feedback capacitors, are checked by applying a signal current from the on-chip circuit. In principle, recording only one measurement per capacitor would be sufficient. However, to increase statistics mainly for the smallest capacitors which tend to be sensitive to operate on the probestation, all combinations are recorded as well. A decreasing gain proportional to the feedback capacitance is expected. This test has produced very stable results with pixels being mostly working, resulting in only 10 erroneous pixels allowed per ASIC.
In the MSDD front-end test, the input transistor and the compression resistor are checked by setting a bias voltage through the periphery DAC and injecting charges into the input node by the internal charge injection. The DAC setting is chosen such that is typically well below the point of highest gain, so a large part of the s-type response can be scanned by the high gain injection. In the evaluation of the data, the slope in the maximum gain region is checked, although a wide range of gains are accepted (3.5± 1.5 ADU/injection step). Up to 100 errors (2.5 % of pixels), as for the
FE2 test, have been allowed here. Due to the strong susceptibility of the input branch on the analog supply, this test has produced a lot of failures, where over 10 % of ASICs had to be discarded.
Using the probestation setup, the input capacitance has been determined for the configuration with floating input balls. The results have been described in section 6.1.7.
It should be noted that the errors from the individual tests may add up to 6 % faulty pixels. In order to exclude the adding up and to get a more precise number of working pixels on each ASIC, the test evaluation software will be upgraded for the successor ASIC, where a bookkeeping table for each pixel will be created.