Design Entry

Start WebPACK ISE Software

Select Start > Programs > Xilinx ISE 5 > Project Navigator

Create a New Project

Select File -> New Project…

Enter the following into the New Project dialogue box:

Project Name: Traffic

Project Location: c:\Designs\Traffic Device Family: Spartan2e

Device: 2S100E

Package: FT256

Speed Grade: -6

Synthesis Tool: XST VHDL

Figure 4.2.1 Project Properties Window CPLD designs

Other device families can be chosen here including CPLDs. For CPLD designs the synthesis tool can also be ABEL XST. Even if the flow is intended to be purely schematic, the schematic diagram will be

Create a 4-bit Counter Module

Use the Language Templates to create a VHDL module for a counter as follows:

From the Project menu select New Source.

Select VHDL Module as the source type and give it a file name

counter.

Click the Next> button.

Fill out the source definition box as follows and then click Next.

Figure 4.2.2 Define VHDL Source Window

This table automatically generates the entity in the counter VHDL module.

Notice a file called counter.vhd has been added to the project in the sources window of the project navigator.

Figure 4.2.3 Counter Window

The source files can be removed from the WebPACK ISE GUI by clicking on the add/remove arrow .

As the project builds you will notice how WebPACK ISE manages hierarchy and associated files in the sources window.

Double clicking on any file name in the sources window will allow that file to be edited in the main text editor.

Figure 4.2.4 Source in project Window

The Language Template

The language template is an excellent tool to assist in creating HDL code. It has a range of popular functions such as counters, multiplexers, decoders and shift registers to assist the designer. There are also

templates for creating common operators (such as ‘IF/THEN’ and ‘FOR’ loops) often associated with software languages.

Language templates are used as a reference. They can be ‘copied and pasted’ into the design, then customised for their intended purpose. Usually, it is necessary to change the bus width or names of the signals or sometimes modify the functionality. In this tutorial the template uses the signal name ‘clk’ and the design requires the signal to be called ‘clock’. The counter in the template is too complex for this particular requirement so some sections are deleted.

Open the Language Templates by clicking the button located on the far right of the toolbar.

The language template can also be accessed from the Edit > Language Template menu.

Click and drag the Counter template from the VHDL -> Synthesis Templates folder and drop it into the counter.vhd architecture between the begin and end statements. An alternative method is to place your cursor between the begin and end statements in

counter.vhd, select Counter in the VHDL > Synthesis Templates folder and the click the

Close the Language Templates.

Notice the colour coding used in the HDL editor. The green text

indicates a comment. The commented text in this template shows which libraries are required in the VHDL header and the port definitions

required if this counter was used in its entirety. As the entity has already been created, this information is not required

Delete the Green Comments

The counter from the template shows a loadable bi-directional counter. For this design only a 4-bit up counter is required

Edit the counter module

• Replace clk with the word ‘clock’ – by using the Edit>Replace function

• Delete the section

if CE='1' then

if LOAD='1' then COUNT <= DIN; else

if DIR='1' then

• Delete the section

else

COUNT <= COUNT - 1; end if;

end if; end if;

The counter module should now look like figure 4.2.5 overleaf.

For the purposes of debugging code, there are several new features available in the source editor window. A right click in the grey bar on the left-hand side of the source editor window will bring up a menu of these features. The line numbers in the side bar can be toggled on or off and bookmarks can be placed to mark lines of interest in the source file.

Figure 4.2.5 Counter in VHDL Window

The above design is a typical VHDL module. It consists of library declarations, an entity and an architecture.

The library declarations are needed to tell the compiler which packages are required.

The entity declares all the ports associated with the design. Count (3 down to 0) means that count is a 4-bit logic vector. This design has 2 inputs clock and reset, and 1 output, a 4-bit bus called ‘count’

The actual functional description of the design appears after the ‘begin’ statement in the Architecture.

The function of this design increments a signal ‘count’ when clock = 1 and there is an event on the clock. This is resolved into a positive edge. The reset is asynchronous as it is evaluated before the clock action. The area still within the Architecture but before the begin statement is where declarations reside. There will be examples of both component declarations and signal declarations later in this chapter.

Save the counter module.

The counter module of the design can now be simulated.

With counter.vhd highlighted in the sources window, the process

window will give all the available operations for that particular module. A VHDL file can be synthesised then implemented through to a bitstream. Normally a design consists of several lower level modules wired

together by a top level file. This design currently only has one module which can be simulated.