Figure 3 tries to depict the general outline of the development flow. During high level design several potential architectures will be examined and block parameters and properties will be swept and explored in order to find the most suited architec- ture and the best according block specifications to be used in that architecture. Since this involves a very wide exploration of the design space that includes the whole system, there is a need for fast simulation/calculation times. This can be obtained
High-level design High-level verification Block design Block design Block design Block layout Block layout Block layout Back annotation Back annotation Back annotation Block specifications Bottom-up verificaton VHDL-AMS model Tape-out
by using very generic first order behavioral models/descriptions for the blocks and use a mathematical signal processing tool.
The high level of abstraction that is needed in the high level design phase makes that there is a need for a separate high level verification step. In this case one tries to verify early on in the development process whether the level of abstraction used during high-level design was sufficient and whether simplification has not resulted in wrong block parameters being selected that will later on, at the end of the devel- opment, prove incorrect because of second order effects that should have been taken into account. A typical well suited tool for such verification work is a mixed signal behavioral description and simulation tool like VHDL-AMS. With careful descrip- tion of the right behavioral model for each block, it allows for in detail system level simulation, while for real open exploration work it may be too time consuming in coding and simulation times that are needed.
In fact, if for high-level verification a tool like VDHL-AMS is used, it makes sense to use VHDL as the high level design tool. Although primarily seen as a digital description language, it is in many cases very well suited for the rapid coding of a serdes architecture. The reason for this is that almost all signals are in fact digital signals of which the most important property is their threshold crossing point and how this is influenced by different factors that introduce jitter (uncertainty on the timing of the crossing point). This can be handled perfectly and with fast enough simulation times with an event driven simulation tool like a VHDL simulator. Ana- log signals present in a serdes often change at a low enough rates such that they can be handled by the event driven simulator without significant deviations. Using VHDL for the high level design will allow an easy step by step increase of the complexity of the behavioral model in VHDL-AMS by introducing such effects as driving and load impedance or coupling. This increased complexity will require that also an adaptive time step solver algorithm is used to perform the simulation. This will result in a significant increase in system simulation time, making that it is best preserved only for the high-level verification process.
Once the architecture has been selected and the building block specifications have been fixed the actual design work at transistor level can start. This will involve the need of a spice like simulator, potentially in combination with an harmonic bal- ance simulator for such properties as phase noise or PSRR. In this transistor level design the availability of a multi-mode simulation tool that allows the combination of the extended high-level behavioral model with gradually replaced parts at tran- sistor level is of utmost importance to be able to rapidly verify whether originally assumed block requirements still hold when taking detailed transistor level block description and properties into account. Moreover it will be important to model early on also power supply lines, package, decoupling etc. and again here a multi-mode simulation tool can allow performing the system level simulations with this level of detail involved for some parts. A point that remains critical in high speed serial data communication design, especially for multi-lane set-ups, is a good way to model substrate coupling and add this to the whole process. Often there is not much more that can be done than use careful heuristic shielding rules and a deep n-well substrate separation strategy.
The top-down bottom-up approach in which behavioral models are gradually re- placed one-by-one by transistor level descriptions can be further extended to include also results from layout back annotation and run these in system level checks.
In the end it is still of vital importance to run full transistor level checks of the whole system with its power supply, package and decoupling model. But complexity will be so large that only very limited checks can be performed, making that they can only serve to check whether the extensive top-down bottom-up check have not neglected an important aspect.