A classic analog approach for Clock and Data Recovery is depicted in Fig. 10a. It uses an analog PLL [14] to synchronize a clock with the data, and uses this clock signal to resample the data. The PLL uses a phase detector (PD) which detects the phase difference between the input data and the clock signal. The PD typically generates an up and a down pulse of which their lengths are proportional to the phase error. These pulses drive a charge pump (CP) which converts the phase error into a current, charging or discharging a capacitance. The charge pump also forms a low pass filter, which stabilizes the loop. The resulting control voltage drives a voltage-controlled oscillator (VCO) towards phase lock.
VCO decision block data detector phase down up lowpass filter charge pump + (a) digital decision block data ε
filter DAC VCO
TDC (b) digital filter decision block data dataout dataout dataout clkout clkout clkout ε DCO TDC (c)
Fig. 10 PLL-based CDR: (a) analog PLL, (b) PLL with a TDC as a digital phase detector, (c)
All-Digital PLL
More digital approaches replace several or all of these blocks with digital ver- sions. Example in Fig. 10b the PD is replaced by a TDC which outputs the phase error as a digital value. The charge pump and low-pass filter are then replaced by a digital filter. Then a D/A Converter converts the result back to the analog control voltage for the VCO.
A next step is even replacing the VCO with a digitally controlled ring oscillator (DCO), leading to an All-Digital PLL (ADPLL) [6–8] (Fig. 10c). The precision of the TDC does not have to be very high, since the TDC error is averaged out by the loop filter. However, higher precision can lead to faster lock times. Despite that, the acquisition time is relatively high because of the closed-loop configuration and PLL-based architectures are considered not suitable for applications that require very fast or even immediate acquisition time.
3.2 Burst-Mode CDR
PLL-based CDR circuits are closed-loop systems, reducing the phase error until a lock is reached between clock and input data. This leads to a long acquisition time,
especially if a wide frequency range is required. In contrast, open-loop systems can have a very fast lock time, and need only a few or even no preamble bits to lock the clock to the incoming data. Most implementations consist of a gated ring oscillator [15, 16] which is triggered by a data edge (see Fig. 11).
The resulting clock is therefore immediately locked with the data edge and can be used to sample the incoming data. The oscillation frequency is locked to the ref- erence clock by using tunable delay elements. However, if this reference frequency deviates too much from the original data clock, recovery is problematic, especially with long runs of 1’s or 0’s. Therefore most of these burst-mode CDRs can only operate at a fixed frequency which must be known in advance. Multirate burst-mode CDRs [17] offer several operation frequencies by using a configurable frequency divider, but they still do not offer a continuous frequency range of operation.
Another technique for burst-mode CDR is using blind oversampling [18, 19] (see Fig. 12). The data is sampled at multiple moments within the clock period. With majority-voting or center-picking, the best sample is selected to be used for the data recovery. As with the gated oscillator, this approach can only work when the data rate is known in advance, since it provides no clock recovery.
data
clkout
Fig. 11 Gated ring oscillator for burst-mode CDR
Fig. 12 Oversampling CDR
data
1 to N
clkref
selector
phase dataout
3.3 Proposed Schematic for an All-Digital TDC-Based
Burst-Mode CDR
Figure 13 presents a new approach for clock and data recovery. It uses a high- precision TDC that measures the location of the data transitions. These mea- surements are fed to a decision block which interprets the data and drives a generation block that simultaneously reconstructs the incoming data and generates
Fig. 13 TDC-based burst-mode CDR 1 to N generator Decision TDC REG data clkref
clkout dataout
t ϕ
a synchronized clock signal along with the output data. Both the TDC and the gen- erator work with multiple phases of a reference clock. Data recovery in this scheme is essentially finding the clock phase closest to the data transitions and using this information to extract a clock signal and to generate the synchronized output data. Since the TDC can instantaneously detect every data transition with high precision, immediate acquisition is possible. Moreover, since the operation of the TDC is inde- pendent on the data rate, this architecture can theoretically handle an infinite range of input frequencies up to the frequency of the reference clock. Hence, it combines the advantage of a flexible input frequency as in PLL-based CDRs, with burst-mode operation.
Figure 14 illustrates the operation of the TDC-based burst-mode CDR for 4 clock phases. For each data edge, the TDC outputs a value t representing the nearest clock phase. This information is then used to reconstruct the data and to generate the output clock. Notice that only two preamble bits (1-0) are sufficient to extract the
ref clock data in send clk data out clock out t=3 t=3 t=3 t=0 TDC output 1 0 1 1 1 0
clock signal and that this information is updated after every new data transition. Even without a preamble, the TDC results can be stored in a register until a 1-0-1 or a 0-1-0 data pattern occurs from which the clock signal can be calculated. After that, data reconstruction can be initiated using the stored data transitions.
The drawback of this method compared to other architectures is that it produces deterministic jitter dependent on the TDC resolution instead of stochastic jitter de- pendent on mismatch and noise. This deterministic jitter occurs every transition and accumulates when the data remains constant, putting a limit on the maximum length of successive 1’s or 0’s that can be correctly processed. E.g. if the data rate is 10 Gb/s and the TDC resolution is 10 ps, the maximum run length is 5, since in the worst case the accumulated error is 50 ps. The extracted clock is then half a period shifted with respect to the original data clock and data can no longer be recovered correctly. However, the precision of the TDC scales along with the technology, so that the deterministic jitter reduces with newer technology nodes.
Table 2 gives an overview of the characteristics of the proposed architecture com- pared with PLL-based and burst-mode CDRs.
Table 2 Comparison of proposed scheme with PLL-based an burst-mode CDRs
PLL-based Burst-mode Proposed
Lock time Very slow Fast Fast
Frequency range limited Fixed data rate Variable data rate
Jitter Stochastic, depends on noise/mismatch Stochastic, depends on noise/mismatch Deterministic, depends on TDC resolution
Scalability Bad Good Good