6.1 Summary
The previous lesson presented how transmission line effects influence the waveform of digital signals. Here we shall review how the designer can manage these effects, in order to guarantee the correctness of information transfer.
This lesson answers the following questions:
• What are the effects of capacitive loads on bus lines?
• What does "IWS driver" mean?
• Which termination circuits are used in real systems?
• What are "parallel" and "series" terminations?
• What is the difference between point-to-point and bused lines?
6.2 Incident wave switching
Incident wave switching (IWS) occurs when the receiver can sense the logic state change on the first step impressed to the line. To guarantee this condition, the first step must be higher than the threshold VTH, and this means Z0 >> RO. This can be obtained by lowering the output resistance RO (that is using high-current drivers), and by keeping the characteristic impedance Z0 as high as possible.
Example 1
The design specifications require to get IWS on an interconnection with:
• Threshold voltage VTH = 2.5 V,
• Characteristic impedance of the interconnection Z0 = 70 ,
• Open circuit output voltage from the driver in the High state: VA = 4 V The designer can derive either the specification for the driver equivalent output resistance RO, or the minimum value for driver output current IOH.
The amplitude of the first incident wave (first step) can be evaluated from the open circuit output voltage, partitioned among the drive output resistance and the line impedance:
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fig 5.1 VB = VA * Z0 / (Z0 + RO), which solved in RO gives:
RO = Z0 * (VA / VB - 1) RO <= 42
An alternate specification is the output current IOH; the voltage VB can be written as:
VB = Z0* IOH
To achieve IWS VB must be higher than the threshold voltage VTH, that is:
IOH = VB / Z0 IOH >= 35,7 mA
6.3 Effects of capacitive loading
The characteristic impedance Z0 depends on the unit capacitance and inductance C' and L':
When new receivers or transceivers are connected to the line (eg in backplane buses, as in figure 5.2), their input parasitic capacitance adds to the intrinsic line
capacitance.
Fig 5.2 Model for a multi-tap interconnection.
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The unit capacitance increases and therefore the characteristic impedance Z0 decreases. If the added unit capacitance is C", the characteristic impedance changes from
to
that is it is reduced by a factor Example 2
A line with characteristic impedance Z0= 70 has unloaded unit
capacitance C' = 50 pF/m (no-load). We connect to the line 20 loads, 30 pF each (equivalent capacitance on a transceiver I/O pin) equally spaced over 50 cm.
What is the new value Z0" of the line characteristic impedance?
The distributed loads account for an additional unit capacitance C" = (30 pF x 20 loads ) / 0.5 m = 1200 pF/m.
The reduction factor is ; therefore Z0" = 70/5 = 14 .
The minimum value for driver output current IOH to achieve IWS (other parameters as in previous example) is now:
VB = Z0" * IOH IOH = VB / Z0 "
IOH >= 178 mA
Such current is far higher than IOH of commercial logic devices.
6.4 Termination circuits
The current flowing in the termination resistance RT must come from (or go into) the driver. In the previous examples the termination resistance RT was always connected to ground. To drive a line with termination
connected to ground at values higher than VTH, the driver must have high IOH. No current is required in the Low State.
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If the termination resistance is tied to VCC (or to any voltage close to VOH), no current flows in the high state and the current is about VOL / RT for the low state. In this case the driver must have high IOL.
For matched lines (RT = Z0) the current may rise to rather high values. For instance, with a termination RT = 70 and VCC = 5 V the output current IOL
= = 70 mA. This current flows into the driver, and adds to receiver input currents.
Due to asymmetry in the output stage, IOL is usually higher than IOH, and therefore termination resistances are usually connected towards VOH rather than to ground. In the case of Open Collector drivers, the termination resistance acts also as pull-up resistance.
Several circuits can be used for terminations; some of them reduce the output current required from the drivers:
6.4.1 Passive termination
This termination is a simple pull-up towards VCC or a termination voltage VT (fig 5.3).
Fig 5.3 Single-resistance termination.
The voltage VT can come from a voltage divider or from a voltage regulator (fig 5.4).
Fig 5.4 Termination to a voltage other than VAL.
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If VT > VOH , the regulator must always supply a current. If VOL < VT < VOH, the regulator must have current sink and source capability. Usual 3 -term regulators (eg the 780x series) are not suitable in this last case; special regulators are available from the manufacturers.
6.4.2 Low power termination
The termination resistance is connected to signal ground though a
capacitor, as in figure 5.5. On a voltage step, the capacitor acts as a short circuit, and the line is terminated by RT . For steady line no current flows in the capacitor, and there is no static power consumption.
Fig 5.5 Passive low-power termination.
6.4.3 Active low power termination circuit.
The non-inverting buffer with positive feedback acts as a bistable circuit which follows the state of the line (fig 5.6). On a state change, current flows in RT only as long as the output has not changed state. For a steady line no voltage difference appears on RT, and no current flows.
Fig 5.6 Active low-power termination.
For any of these circuits, diodes connected to ground or to the power supply clamps spikes caused by reflected waves or by reactive devices (fig 5.7).
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Fig 5.7 Clamping the far end to block noise spikes.
6.5 Driving point-to-point lines
This section describes the signals in transmission lines driven from one end. The first case discussed is a line open at the far end ( T = 1) and matched at the driver (RO = Z0).
The first step in B (t = 0) has amplitude VA/2 (partition of VA on RO and Z0).
At t = tP the first step reaches the far end (C), and is incremented by the reflected wave (with the same amplitude, since T = 1). The total step is twice the first step in B. At 2 tP the reflected wave comes back to the near end (B) and adds to the first step.
The system is now in its final state; there is no further reflection because the driver side of the line is matched. The waveforms are in figure 5.8 (where 1 tP corresponds to 2.5 horizontal divisions).
Fig 5.8 Near end (top trace ) and far end waveforms for an open
line with matched driver.
We will now analyse the same circuit as in the previous example (line open at the far end: T = 1, with the driver no longer matched (RO < Z0,
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G < 0). Such mismatching occurs whenever we use high current drivers to get a high first step, because of their low equivalent output resistance.
Since G < 0, the signal reflected at the driver has opposite polarity with respect to the original step. The steps on the line can be either positive or negative, with sign inversion every 2 tP, (the time distance between reflections at driver).
At the far end C, where incident and reflected wave sum with the same polarity, the actual waveform can oscillate. These oscillations may bring the voltage to cross several times the logic threshold VTH, thus causing additional logic state changes.
Fig 5.9 Near end (top trace) and far end waveforms for an open line with high-current, low-resistance driver.
To avoid unwanted logic state changes caused by high current drivers we could match the line at the far end. This parallel termination is a load, and increases static power consumption.
Another possibility to block oscillations is to match the line at the driver side, with a resistance RG connected between the line and the driver output, as in figure 5.10. If RG + RO = Z0, the total equivalent resistance at the driver side is RO' = Z0, and the backward wave (travelling from C to B) is fully absorbed at the driver.
Fig 5.10 Series termination.
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At the driver side we can observe a double step (incident wave at t=0, reflected wave at t = 2 tP; on the open end we get a single step with double size (incident plus reflected wave) at t = tP.(Figure 5.11).
This technique is called series termination, and is widely used to drive address and control lines of small memory banks. It uses less power then parallel termination at the far end, but can be used only for point-to-point interconnections, driven from one end.
Fig 5.11 Open line, low resistance driver with series termination.
6.6 Driving bused lines
A driver connected to an intermediate point E of a uniform line with
characteristic impedance Z0 is loaded by an impedance Z0/2 (Fig 5.12). To get incident wave switching, the driver output impedance must be very low (that is, the driver must be able to source or sink a high current). In the node E we have three parallel branches, respectively with impedance Z0, Z0, and RO. The equivalent impedance in E is always less that Z0, and the corresponding reflection coefficient < 0. The polarity of reflected waves is inverted and the voltage on the line can oscillate as in the previous example.
Since another branch of the line is connected at driver output, source termination in the node E is not possible (Z0 in parallel to any other impedance is always less than Z0). To absorb the reflections it is necessary to terminate the line at both ends. This is the typical case of multipoint b uses (for instance backplane buses, where several boards can be connected at many positions).
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Fig 5.12 Line driving from an intermediate point.
In multi-point buses, many devices (active driver, receiver, disabled drivers, and passive loads) are tied to each line. The capacitive load lowers the propagation speed and the characteristic impedance of the line (a 100 line can go below 20 due to additional capacitance; the
propagation speed scales the same factor). Driving low impedance lines requires high-current devices, and high current means more heat to dissipate and more noise towards other circuits (that is a EMC problem).
Therefore it is mandatory design practice to limit the capacitive load on each line.
The board must use a single transceiver towards the bus (figure 5.13, left).
The transceiver isolates all on-board circuits and reduces the capacitive loading on bus lines. Direct connection of on-board devices to bus lines (figure 5.13, right) must be avoided, since it increases the capacitive load and lowers the characteristic impedance.
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Fig 5.13 Interfacing a daughter- board with a backplane bus.
L and C parasitic parameters are proportional to track length; to keep them to minimum values, the transceiver must be placed as close as possible to the board connector. For the same reason the smallest acceptable package should be used; SMD devices are preferred towards PTH (figure 5.14), because of smaller size and shorter pin connections which keeps low parasitic capacitance and inductance.
Pin Though Hole (PTH) devices Surface Mount Devices(SMD) Fig 5.14 Comparison among different packages.
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6.7 Design guidelines
High-speed logic systems must use multiple layer Printed Circuit Boards (PCBs), with alternated signal layer and ground/supply layers, to provide a controlled environment for signal propagation. Example of signal track layers and ground plane are in figure 5.15.
Fig 5.15 Tracks and ground plane in a PCB.
In summary, to get high transfer speed and reliability in a multipoint bus connection we must:
• limit capacitive loading by inserting isolation buffers on each board;
• place drivers and receivers as close as possible to the bus connector;
• choose small packages, with low parasitics;
• use multilayer PCB, to get a well defined transmission line environment.
6.8 Review questions
1) The correct value of a series termination resistance RS is:
(RO is the output resistance of the driver; Z0 the line impedance, RT the
The sum of driver output resistance and external series termination must equal the line characteristic impedance.
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2) To avoid reflections with mid-point driving bused lines, one has to:
leave line ends open,
put series termination on all drivers,
*place matched parallel termination at both ends, place matched parallel termination at one end only.
Since three branches (two transmission lines and the driver output) converge at the driving node, it is not possible to match the line at the driver side. The only possibility is to avoid reflections at the far ends, by matched terminations.
3) In a mid-point driven 100 ohm bused line, the amplitude of the first step, for VA = 5 V, RO = 50 , is:
4) A 20cm PCB track with unit capacitance 30 pF/m is loaded with 10 loads with equivalent capacitance 10 pF, evenly spaced. The unloaded line impedance is 150 . The approximated loaded line impedance is:
• 200 ,
• 100 ,
• 10 ,
• *35 .
The loaded line impedance can be calculated as: ; since the unloaded impedance is the impedance reduction factor is
.
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The added unit capacitance is C" = ((10 x 10 pF) / 20cm ) x 100cm) = 500 pF/m.
Loaded line impedance Z" = 150/4.2 = 35.68 .
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