SOLUTION SPACE ANALYSIS

The steps involved in performing solution space analysis are:

1. Define an initial topology (placement/routing strategy) for a class of high-speed nets 2. Define the different manufacturing tolerances to be analyzed, and their min/max values 3. Define the starting point for the design variances to be analyzed

4. Set up and run a number of simulation cases

5. Examine the simulation results, identify which cases “failed” and why 6. Adapt the topology and design rules as appropriate

7. Repeat steps 4-6 until the topology “converges” on a set of values that “pass” for all cases analyzed 8. Derive design rules for the target CAD system

9. Use the resulting rules to drive the placement/routing processes

12.3.1 STEP 1 — DEFINING THE INITIAL TOPOLOGY

Solution space analysis starts by defining pin scheduling, termination (if any) and nominal circuit parameters for a representative high-speed net. If the net is part of a high-speed bus, then all the bits of the bus will typically have the same electrical/physical constraints, such that finding a routing solution for one bit of the bus constitutes finding a solution for the whole bus. If there are any pre-existing constraints for device placement, they should be taken into account at this stage. For example, if the processor cannot be less than 3” away from its corresponding chipset, it makes no sense to explore potential routing strategies with processor — chipset connections less than 3” in length. By taking known placement constraints into account up front, electrically valid (but physically invalid) solutions can be eliminated early.

12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES

The next step is to determine which manufacturing tolerances will have a significant effect on the behavior of the circuit. For instance, the typical +/- 10% variance in characteristic impedance of an impedance-controlled board may have a substantial effect on SI, while the +/- 1% variation in the impedance of a precision terminator may not. Because solution space analysis looks at all

combinations of variables, it makes sense to analyze only those variances that are “significant,” in which “significant” is a design–specific factor. Sensitivity analysis can be performed at this stage to help prioritize the effect of the different manufacturing variances on circuit behavior. This helps identify which variables can be excluded, or left until a final, detailed validation is to be performed.

Other optimizations can also help reduce simulation run time and improve accuracy –for example, if multiple segments of the same net are routed on the same signal layer, the impedance of the

different segments will “track” (scale together). Modeling this tracking behavior has the benefit of reducing the number of different cases that need to be analyzed, and eliminating unnecessary pessimism in the results. Once the variables to be analyzed and their values are determined, the min/max data is entered as part of the circuit model.

PCB Designer’s SI Guide Page 136 Venkata 12.3.3 STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES

Recall that the design variances will ultimately become the “design rules” used for PCB layout.

These rules can be specified as physical rules (net length, spacing), as well as electrical rules (segment delay, overshoot, crosstalk) – or as a combination of both. Once determined, the different design variables and their min/max values are entered as part of the circuit model.

Some design rules may involve a relationship between different parts of the net. For instance, if two net segments are required to always total to a certain length, the delay of one length should be expressed as a function of the length of the other segment. This is a similar form of optimization to the one discussed in step 2, in that this reduces the simulation run time and improves the accura cy of the results.

12.3.4 STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES

Once the circuit and its variables/relationships are set up, the process of defining all the different cases (combinations of variables) and analyzing them should be fairly automatic. This will be

dependent on the CAD software user for analysis. Traditional solution space analysis processes have relied on collections of commercial tools and custom “scripts” to perform this process. In the Cadence 13.6 release, Signal Explorer Expert performs this process automatically. The number of cases to be analyzed grows rapidly as additional variables are introduced, and can rapidly expand to require millions of simulation runs. To keep run times down and simulations practical, some method of randomly running “subsets” of the full simulation job is required.

This serves two purposes:

1. It keeps the number of simulation runs manageable for large, multi-variable runs.

2. It allows small subsets of a large analysis job to be run quickly to identify problems, saving the large runs for later after the topology has converged.

12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY

Solution space analyses are typically run as batch jobs that take anywhere from 5 minutes to many hours. They return simulation results for each case analyzed — usually in terms of electrical

parameters like calculated flight time, overshoot, etc. The simulation results are compared against a design requirement to determine which cases passed and which failed. For instance, the timing budget might show that the flight time for a high-speed net must be greater than 300pS, and less than 3.2nS, while electrical constraints might require that overshoot be limited to less than 500mV.

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Figure 2. Example of multi-case analysis and results display

Sorting and filtering the simulation results makes it easy to identify which cases failed, and which combinations of conditions they represent.

12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE

Once the passing/failing cases have been identified, the electrical designer examines the results and determines how to correct the topology. Sorting, filtering and plotting the data may make it easier to spot the “trends” that determine electrical success or failure. The designer may also want to isolate a specific case and rerun the detailed simulation to view the simulation waveforms to aid in debugging.

Based on the simulation data, the topology being designed and an understanding of the high-speed phenomena affecting the circuit, the designer makes an adjustment to the topology and reruns the process.

12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED

The solution space process is iterative, thus, the layout-analyze-fix loop has been moved all the way forward in the design cycle. This process continues until the topology converges into a set of design variances that allow the design to function correctly under all combinations of real-world conditions.

Keep in mind that not all topologies will converge. Failure to converge may indicate that a

placement/routing strategy is simply not viable, and that different placement/routing/termination rules should be investigated.

12.3.8 STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM

After a solution space analysis is defined, the electrical designer determines the applicable design rules for layout. The “real world” variances used in solution space analysis are not passed to layout, because the analysis accounted for the actual variances in the manufactured design (e.g. trace impedance) even when the designer tried to keep the value fixed. The design rules passed to layout are determined by the design variances (e.g. min/max segment length) used in solution space analysis.

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Figure 3. Example of circuit topology and associated rules

12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES

This step has traditionally been a large “disconnect” in high-speed PCB design, because the design rules are only passed verbally or on paper, but not as a part of the fundamental PCB database itself How the design rules can be passed to layout will be highly CAD system dependent. Ideally, all the rules for a given set of nets can be collected into a generic “template” that defines the routing strategy for the entire group of nets. Pin scheduling, min/max segment lengths (either electrical or physical), length matching restrictions and any other electrical/physical requirements are encoded a s part of the template. The template is then imprinted against a group of nets in the PCB database, imposing the associated design rules on each net in the group. This template strategy proves

especially useful for managing large buses, in that a single template can be used to quickly specify all the design rules across the entire bus.

If the design rules can be expressed as rules supported by the CAD tool, then the native design-rule-check (DRC) capabilities of the native CAD system can be used to ensure the physical design is compliant with the defined design rules. This represents a considerable — though not necessarily obvious — improvement over the traditional technique of running post-layout SI analysis to

uncover high-speed signal problems. For example, if the design rule for a given segment specifies an electrical length of not more than 500 pS, and the segment was manually routed to be 750 pS in length, then should be no need to run a full SI analysis to uncover what is really a simple length violation – since the DRC capabilities of almost all CAD tools support simple length checks.

Thus, the native DRC capabilities of the CAD system can be used to pinpoint basic design rule violations so they can be quickly resolved. In an ideal situation, a rules-based autorouter would simply route the design to specifications.

In practice however, design is performed as a combination of auto/cleanup routing and interactive routing. DRCs are created early in the process and cleaned up as the design progresses. DRCs offer the quickest and most efficient way to highlight and resolve problems. By leveraging the CAD tool’s DRC system, most errors are found early, leaving only the more difficult (and unexpected) design issues for SI analysis.

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This strategy of using solution space analysis up front to define rules and then driving them into the layout system opens up possibilities for new design tools. For example, a spreadsheet display can be used to show the different constraints contained in the database, and provide a real-time display of how the design compares against those constraints as the design is placed and routed. During placement, the spreadsheet can provide feedback of the different tradeoffs involved in component placement as each component is moved.

Figure 4. Spreadsheet analysis of design constraints based on placement

In an ideal world, design rules would be defined completely before placement and routing began. In the real world, design rules are usually not completely defined before physical design begins, and almost always change as the design and routing process progresses. If the CAD system allows new design rule templates to be applied against the existing design without disturbing the

placement/routing, CAD designers can quickly assess the impact of changes in design rules against existing work, identifying which signals will need to be rerouted, and the degree to which those nets violate the updated design rules.

An additional advantage of this technique is that SI analysis need not be rerun every time the routing of a critical net is updated. Because the design rules were determined from up-front comprehensive analysis of worst-case conditions, any net routing that conforms to the design rules in the database can be expected to function correctly.

12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS

Post-layout SI analysis still has its place in a solution space design flow, because unexpected problems can still occur. The emphasis shifts considerably, because the post-layout analysis is intended to serve as a “signoff” analysis, instead of being used as the primary vehicle for identifying SI issues. The problems uncovered during post-layout analysis, if any, tend to be isolated and correctable on a case-by-case basis.

12.4 CONCLUSION

This article has reviewed the traditional techniques for identifying SI problems in high-speed designs, and outlined the “solution space” approach for defining and driving high-speed placement and routing strategies. This technique uses comprehensive up-front SI analysis to define robust

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design rules, and then leverages the CAD system’s native design rule checks to ensure that the design is placed and routed according to the design rules.

While the solution space approach has been used by semiconductor vendors for years, it has re lied heavily on custom methodologies and scripting designed around specific design scenarios. The capability to provide this type of analysis to the average user has only recently become available in commercial SI tools. high-speed design issues invariably require changing the PCB design process. Because the issues of signal timing, signal integrity, power delivery/decoupling and EMI are interrelated, the PCB electrical and physical design processes must become interrelated as well. The solution space approach takes advantage of the different groups of engineers that exist in most organizations and their respective strengths. Up-front and post-route SI analysis can be performed by electrical designers, who derive electrical design rules based on SI analysis and an understanding of the preexisting placement requirements of a design. By imprinting the resulting design rules into the PCB database and leveraging the CAD tool’s DRC capabilities, layout designers have the best chance of routing the design to the ru les, and can choose from a selection of interactive and automatic routing strategies.

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13 Glossary

Word Definition

AC Coupling

Method of interfacing drivers and receivers through a series capacitor. Often used when the differential swing between drivers and receivers is compatible, but common mode voltages of driver and receiver are not. Requires that a minimum data frequency be established based on the RC time constant, necessitating a run length limit.

Attenuation Reduction in amplitude of a signal.

BER See Bit Error Rate

BERT See Bit Error Rate Test or Bit Error Rate Tester

Bit Error Rate

A measurement of the number of errors detected at a receiver in a given length of time, sometimes specified as a percentage of received bits;

sometimes specified in exponential form (10E-8 to indicate 1 bit error in 10E-8 bits).

Bit Error Rate Test or Bit Error Rate Tester

An instrument used to determine the Bit Error Rate (BER) of a device or system under test. It is generally made up of a test pattern generator, receiver, and analyzer.

BIST Built-In Self Test

CDR See Clock Data Recovery.

Channel Bonding Feature of multi-channel high-speed transceivers. Allows multiple channels to be sued together, offering a greater aggregate bandwidth.

Chirp

Bit sequence, which is transmitted by a high-speed transceiver when it is not in use. The chirp is usually a repeating pattern of IDLE characters. The purpose of the chirp is to keep clock recovery circuits aligned and active while the link is not transmitting data.

Clock/Data Recovery

Feature of most high-speed serial transceivers. At the receiver, a clock is generated based on the timing of data transitions. In this way, a clock signal is derived from the data.

CML See Current Mode Logic.

Comma K-character

Common Mode The DC component of a signal. In differential channels, it is the average voltage of the differential pair.

Crosstalk

Undesirable signal coupling from noisy aggressor nets to victim nets. May be eliminated by increasing the spacing between the nets or reducing signal amplitude of the aggressor net.

Current Mode Logic A differential I/O standard used in high-speed serial channels. Voltage swing is typically from 450 mV to 1200 mV.

DC Balanced

A channel is said to be DC Balanced if it has an equal number of 1’s and 0’s transmitted across it. Encoding schemes like 8B10B are designed to ensure this.

DC Coupling Method of interfacing drivers and receivers without the use of series capacitors. A direct connection (through PCB trace) from driver to receiver.

Deterministic Jitter

The component of jitter attributable to the data pattern in the channel.

Different digital patterns have different spectral contents. These differing spectral contents give rise to varying amounts of signal jitter.

Differential Signaling A signaling scheme, which uses two complementary signals to transmit data.

PCB Designer’s SI Guide Page 142 Venkata Differential signaling offers faster data rates at reduced signal swing, with higher signal to noise ratio.

Dispersion

"Smearing" of a signal or waveform as a result of transmission through a non-ideal transmission line. Through a non-non-ideal medium, signals travel at different velocities according to their frequency. Dispersion of the signal is the result.

All cables and PCB transmission lines are non-ideal.

DSL Digital Subscriber Line

Equalization Amplification or attenuation of certain frequency components of a signal. Used to counteract the effects of a non-ideal transmission medium.

Eye Diagram

An eye diagram of a signal overlays the signal’s waveform over many cycles.

Each cycle’s waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. It can be generated by synchronizing an oscilloscope to a timing reference.

The vertical thickness of the line bunches in an eye diagram indicate the magnitude of AC voltage noise, whereas the horizontal thickness of the bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen.

Eye Mask

The size of the eye opening in the center of an eye diagram indicates the amount of voltage and timing margin available to sample this signal. Thus, for a particular electrical interface, a fixed reticule or window could be placed over the eye diagram showing how the actual signal compares to minimum criteria window, know as the eye mask. If a margin rectangle with width equal to the required timing margin and height equal to the required voltage margin fits into the opening, then the signal has adequate margins. Voltage margin can often be traded of for timing margin.

Falltime

The time it takes for a waveform to transition from the high logic state to the low logic state. Falltime is usually measured from 90% of the total signal swing to 10% of the signal swing.

Idle Pattern

A data sequence transmitted by a high-speed transceiver as a placeholder or for link maintenance. The particular sequence of an IDLE pattern is

determined by the communication protocol, and is usually a control character like K28.5.

Impedance (Characteristic Impedance)

Electrical characteristic of a transmission line, derived from the capacitance and inductance per unit length.

Inter-Symbol Interference A form of data corruption or noise due to the effect that data has on data-dependent channel characteristics.

ISI See Inter-Symbol Interference.

Jitter

The jitter of a periodic signal is the delay between the expected transition of

The jitter of a periodic signal is the delay between the expected transition of

In document PCB Designer’s SI Guide (Page 135-144)