IP Core
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2016.07.22
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The CPRI v6.0 IP core achieves low latency and lower resource utilization than the legacy CPRI IP core and provides new interfaces for direct access to the CPRI frame. The signals, registers, and register fields are different: you cannot simply substitute the new IP core for the legacy IP core in your design without additional design work.
To compare the CPRI v6.0 IP core to previous releases of the CPRI IP core, refer to the table and to the Altera documentation about the revision history of the CPRI IP core.
Table A-1: Major Differences Between the CPRI v6.0 IP Core and the CPRI IP Core
The Altera CPRI IP core is a product available through several previous Altera software releases. The differences in signals, registers, and register fields are too numerous to list in this table.
The comparison is defined relative to the version of the legacy CPRI IP core available with the Altera software release v14.0.
Property CPRI v6.0 IP Core CPRI IP Core
CPRI specification Complies with the CPRI
Specification V6.0 (2014-08-30). Complies with the CPRI Specifi‐cation V5.0 (2011-09-21). IP core installation IP core is available for installation
and integration into your ACDS installation from the Altera Self- Service Licensing Center.
IP core is included in Altera MegaCore IP Library.
Device support Supports Arria 10, Arria V GX, Arria V GT, Arria V GZ, Cyclone V, and Stratix V device families.
Supports Arria II (GX and GZ), Arria V (GX, GT, and GZ), Cyclone IV GX, Cyclone V GX, Stratix IV GX, and Stratix V device families.
CPRI line bit rate Supports CPRI line bit rates through
10.1376 Gbps. Supports CPRI line bit ratesthrough 9.8304 Gbps.
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Property CPRI v6.0 IP Core CPRI IP Core Ethernet MAC Optionally includes an Ethernet PCS
block that communicates with user logic through an IEEE 802.3 100BASE-X 100Mbps MII or an IEEE 802.3 1000BASE-X 1Gbps MII.
Optionally includes an Ethernet MAC block that communicates with user logic through registers. If you do not include the
Ethernet MAC, user logic can communicate with the internal Ethernet PCS block through an MII-like interface.
HDLC Supports optional HDLC serial
direct connection to Layer 1. Optionally includes an HDLCblock that communicates with user logic through registers. Direct access to CPRI frame Supports AUX interface for direct
access to full CPRI frame, with optional specified write latency. Also supports individual interfaces for direct access to I/Q data bytes only, to Ctrl-AxC bytes only, to VSS bytes only, and for 10.1376 Gbps
variations, to RTVS bytes only, with same optional specified write latency. You can configure any combination of these interfaces. Optionally supports register access to all control words in CPRI frame.
Supports AUX interface for direct access to full CPRI frame. Optionally supports register access to all control words in CPRI frame.
I/Q Mapping Supports direct IQ interface to access the I/Q bytes in the CPRI frame.
Optionally includes an I/Q mapper that supports certain wireless standards. For direct access to IQ data in the CPRI frame, only the AUX interface is available.
Start-Up Sequence State
Machine Optionally includes a state machinethat controls the start-up sequence. Optionally includes negotiation of protocol version and Layer 2 Control and Management rates.
Requires that software control start-up sequence, including negotiation of protocol version and Layer 2 Control and Management rates. Debug and Alarm Signals Optional additional debug interface
and optional interface for access to all five Z.130.0 alarms.
Signals to control and monitor Z. 130.0 reset requests.
Related Information
• CPRI MegaCore Function User Guide
For detailed information about changes to top-level interfaces in different versions of the legacy CPRI IP core, refer to the Document Revision History in the Additional Information chapter.
A-2 Differences Between CPRI v6.0 IP Core and CPRI IP Core UG-20008 UG-200082016.07.22
• Altera IP Release Notes
For information about changes in different versions of the legacy CPRI IP core, refer to the Product Revision History in the CPRI MegaCore function chapter. The CPRI v6.0 is not included in the MegaCore IP library and therefore, is not included in this document.
UG-20008 UG-20008
2016.07.22 Differences Between CPRI v6.0 IP Core and CPRI IP Core A-3
Differences Between CPRI v6.0 IP Core and CPRI IP Core Altera Corporation