Digital Signals and Systems

DSP Fundamentals and Implementation Considerations

The derivation of discrete-time systems is based on the assumption that the signal and system parameters have infinite precision. However, most digital systems, filters, and algorithms are implemented on digital hardware with finite wordlength. Therefore DSP implementation with fixed-point hardware requires special attention because of the potential quantization and arithmetic errors, as well as the possibility of overflow.

These effects must always be taken into consideration in DSP system design and implementation.

This chapter presents some fundamental DSP concepts in time domain and practical considerations for the implementation of digital filters and algorithms on DSP hard-ware. Sections 3.1 and 3.2 briefly review basic time-domain DSP issues. Section 3.3 introduces probability and random processes, which are useful in analyzing the finite-precision effects in the latter half of the chapter and adaptive filtering in Chapter 8. The rigorous treatment of these subjects can be found in other DSP books listed in the reference. Readers who are familiar with these DSP fundamentals should be able to skip through some of these sections. However, most notations used throughout the book will be defined in this chapter.

3.1 Digital Signals and Systems

In this section, we will define some widely used digital signals and simple DSP systems.

The purpose of this section is to provide the necessary background for understanding the materials presented in subsequent sections and later chapters.

3.1.1 Elementary Digital Signals

There are several ways to describe signals. For example, signals encountered in com-munications are classified as deterministic or random. Deterministic signals are used

Real-Time Digital Signal Processing. Sen M Kuo, Bob H Lee Copyright # 2001 John Wiley & Sons Ltd ISBNs: 0-470-84137-0 (Hardback); 0-470-84534-1 (Electronic)

for testing purposes and for mathematically describing certain phenomena. Random signals are information-bearing signals such as speech. Some deterministic signals will be introduced in this section, while random signals will be discussed in Section 3.3.

As discussed in Chapter 1, a digital signal is a sequence of numbers fx…n†, 1 < n < 1g, where n is the time index. The unit-impulse sequence, with only one non-zero value at n ˆ 0, is defined as

d…n† ˆ 1, n ˆ 00, n 6ˆ 0,



…3:1:1†

where d…n† is also called the Kronecker delta function. This unit-impulse sequence is very useful for testing and analyzing the characteristics of DSP systems, which will be discussed in Section 3.1.3.

The unit-step sequence is defined as

u…n† ˆ 1, n  00, n < 0:



…3:1:2†

This signal is very convenient for describing a causal (or right-sided) signal x…n†

for n  0. Causal signals are the most commonly encountered signals in real-time DSP systems.

Sinusoidal signals (sinusoids or sinewaves) are the most important sine (or cosine) signals that can be expressed in a simple mathematical formula. They are also good models for real-world signals. The analog sinewave can be expressed as

x…t† ˆ A sin…Vt ‡ f† ˆ A sin…2pft ‡ f†, …3:1:3†

where A is the amplitude of the sinewave,

V ˆ 2pf …3:1:4†

is the frequency in radians per second (rad/s), f is the frequency in Hz, and f is the phase-shift (initial phase at origin t ˆ 0) in radians.

When the analog sinewave defined in (3.1.3) is connected to the DSP system shown in Figure 1.1, the digital signal x(n) available for the DSP hardware is the causal sinusoidal signal

x…n† ˆ A sin…VnT ‡ f†, n ˆ 0, 1, . . . , 1

ˆ A sin…VnT ‡ f†u…n†

ˆ A sin…2pfnT ‡ f†u…n†, …3:1:5†

where T is the sampling period in seconds. This causal sequence can also be expressed as

x…n† ˆ A sin…!n ‡ f†u…n† ˆ A sin…2pFn ‡ f†u…n† , …3:1:6†

where

! ˆ VT ˆV

f_s …3:1:7†

is the discrete-time frequency in radians per sample and F ˆ f T ˆf

f_s …3:1:8†

is the normalized frequency to its sampling frequency, fs, in cycles per sample.

The fundamental difference between describing the frequency of analog and digital signals is summarized in Table 3.1. Analog signal sampling implies a mapping of an infinite range of real-world frequency variable f (or V) into a finite range of discrete-time frequency variable F (or !). The highest frequency in a digital signal is F ˆ 1=2 (or

! ˆ p) based on Shannon's sampling theorem defined in (1.2.3). Therefore the spectrum of discrete-time (digital) signals is restricted to a limited range as shown in Table 3.1.

Note that some DSP books define the normalized frequency as F ˆ f

… f_s=2† with frequency range 1  F  1.

Example 3.1: Generate 64 samples of a sine signal with A ˆ 2, f ˆ 1000 Hz, and fsˆ 8 kHzusing MATLAB. Since F ˆ f =fsˆ 0:125, we have ! ˆ 2pF ˆ 0:25p.

From Equation (3.1.6), we need to generate x…n† ˆ 2 sin…!n), for n ˆ 0, 1, . . . , 63.

These sinewave samples can be generated and plotted by the following MATLAB script:

n ˆ [0:63];

omega ˆ 0.25*pi;

xn ˆ 2*sin(omega*n);

plot(n, xn);

3.1.2 Block Diagram Representation of Digital Systems

A DSP system (or algorithm) performs prescribed operations on digital signals. In some applications, we view a DSP system as an operation performed on an input signal, x(n), in order to produce an output signal, y(n), and express the general relationship between x(n) and y(n) as

Table 3.1 Units, relationships, and range of four frequency variables

Variables Unit Relationship Range

V radians per second V ˆ 2pf 1 < V < 1

f cycles per second (Hz) f ˆF

T 1 < f < 1

! radians per sample ! ˆ 2pF p  !  p

F cycles per sample F ˆf

fs

1

2 F 1 2

DIGITAL SIGNALS AND SYSTEMS 79

y…n† ˆ T‰x…n†Š, …3:1:9†

where T denotes the computational process for transforming the input signal, x(n), into the output signal, y(n). A block diagram of the DSP system defined in (3.1.9) is illustrated in Figure 3.1.

The processing of digital signals can be described in terms of combinations of certain fundamental operations on signals. These operations include addition (or subtraction), multiplication, and time shift (or delay). A DSP system consists of the interconnection of three basic elements ± adders, multipliers, and delay units.

Two signals, x1…n† and x2…n†, can be added as illustrated in Figure 3.2, where

y…n† ˆ x1…n† ‡ x2…n† …3:1:10†

is the adder output. With more than two inputs, the adder could be drawn as a multi-input adder, but the additions are typically done two multi-inputs at a time in digital hard-ware. The addition operation of Equation (3.1.10) can be implemented as the following C55x code using direct addressing mode:

mov @x1n, AC0 ; AC0 ˆ x1(n)

add @x2n, AC0 ; AC0 ˆ x1(n)‡x2(n) ˆ y(n)

A given signal can be multiplied by a constant, a, as illustrated in Figure 3.3, where x(n) is the multiplier input, a represents the multiplier coefficient, and

y…n† ˆ ax…n† …3:1:11†

x(n) DSP system

T [ ]

y(n) = T [x(n)]

Figure 3.1 Block diagram of a DSP system

x₁(n) x₁(n)

x₂(n) + y(n) x₂(n) y(n)

+ Σ

or

Figure 3.2 Block diagram of an adder

x(n) a y(n)

or

x(n) a y(n)

Figure 3.3 Block diagram of a multiplier

x(n) y(n) = x(n−1) z⁻¹

Figure 3.4 Block diagram of a unit delay

is the multiplier's output. The multiply operation of equation (3.1.11) can be imple-mented by the following C55x code using indirect addressing mode:

amov #alpha, XAR1 ; AR1 points to alpha () amov #xn, XAR2 ; AR2 points to x(n) mpy *AR1, *AR2, AC0 ; AC0 ˆ *x(n) ˆ y(n)

The sequence {x…n†} can be shifted (delayed) in time by one sampling period, T, as illustrated in Figure 3.4. The box labeled z ¹ represents the unit delay, x(n) is the input signal, and

y…n† ˆ x…n 1† …3:1:12†

is the output signal, which is the input signal delayed by one unit (a sampling period).

In fact, the signal x…n 1† is actually the stored signal x(n) one sampling period (T seconds) before the current time. Therefore the delay unit is very easy to implement in a digital system, but is difficult to implement in an analog system. A delay by more than one unit can be implemented by cascading several delay units in a row. Therefore an L-unit delay requires L memory locations configured as a first-in first-out buffer, which can also be implemented as a circular buffer (will be discussed in Chapter 5) in memory.

There are several ways to implement delay operations on the TMS320C55x. The following code uses a delay instruction to move the contents of the addressed data memory location into the next higher address location:

amov #xn, XAR1 ; AR1 points to x(n)

delay *AR1 ; Contents of x(n)is copied to x(n 1)

These three basic building blocks can be connected to form a block diagram repre-sentation of a DSP system. The input±output (I/O) description of a DSP system consists of mathematical expressions with addition, multiplication, and delays, which explicitly define the relationship between the input and output signals. DSP algorithms are closely related to block diagram realizations of the I/O difference equations. For example, consider a simple DSP system described by the difference equation

y…n† ˆ ax…n† ‡ ax…n 1†: …3:1:13†

The block diagram of the system using the three basic building blocks is sketched in Figure 3.5(a). Note that the difference equation (3.1.13) and the block diagram show exactly how the output signal y(n) is computed in the DSP system for a given input signal, x(n).

The DSP algorithm shown in Figure 3.5(a) requires two multiplications and one addition to compute the output sample y(n). A simple algebraic simplification may

DIGITAL SIGNALS AND SYSTEMS 81

y(n) Σ

+ + a a

(a)

Σ y(n)

+ + a

x(n) x(n−1)

x(n) x(n−1)

z⁻¹ z⁻¹

(b)

Figure 3.5 Block diagrams of DSP systems: (a) direct realization described in (3.1.13), and (b) simplified implementation given in (3.1.14)

be used to reduce computational requirements. For example, (3.1.13) can be rewritten as

y…n† ˆ a‰x…n† ‡ x…n 1†Š: …3:1:14†

The block diagram implementation of this difference equation is illustrated in Figure 3.5(b), where only one multiplication is required. This example shows that with careful design (or optimization), the complexity of the system (or algorithm) can be further reduced.

The C55x implementation of (3.1.14) can be written as:

amov #alpha, XAR1 ; AR1 points to  amov #temp, XAR2 ; AR2 points to temp mov *(x1n), AC0 ; AC0 ˆ x1(n)

add *(x2n), AC0 ; AC0 ˆ x1(n)‡x2(n)

mov AC0, *AR2 ; Temp ˆ x1(n)‡x2(n), pointedby AR2 mpy *AR1, *AR2, AC1 ; AC1 ˆ ^[x1(n)‡x2(n)]

Equation (3.1.14) can also be implemented as:

amov #x1n, XAR1 ; AR1 points to x1(n) amov #x2n, XAR2 ; AR2 points to x2(n) amov #alpha, XAR3 ; AR3 points to  mpy *AR1, *AR3, AC1 ; AC1 ˆ ^x1(n)

mac *AR2, *AR3, AC1 ; AC1 ˆ ^x1(n) ‡ ^x2(n)

When the multiplier coefficient a is a number with a base of 2 such as 0.25 (1/4), we can use shift operation instead of multiplication. The following example uses the absolute addressing mode:

mov *(x1n)#-2, AC0 ; AC0 ˆ 0.25*x1(n)

add *(x2n)#-2, AC0 ; AC0 ˆ 0.25*x1(n) ‡ 0.25*x2(n)

where the right shift option, #-2, shifts the content of x1n and x2n to the right by 2 bits (equivalent to dividing it by 4) before they are used.

3.1.3 Impulse Response of Digital Systems

If the input signal to the DSP system is the unit-impulse sequence d…n† defined in (3.1.1), then the output signal, h(n), is called the impulse response of the system. The impulse response plays a very important role in the study of DSP systems. For example, consider a digital system with the I/O equation

y…n† ˆ b₀x…n† ‡ b₁x…n 1† ‡ b₂x…n 2†: …3:1:15†

The impulse response of the system can be obtained by applying the unit-impulse sequence d…n† to the input of the system. The outputs are the impulse response coeffi-cients computed as follows:

h…0† ˆ y…0† ˆ b₀
1 ‡ b₁
0 ‡ b₂
0 ˆ b₀ h…1† ˆ y…1† ˆ b0
0 ‡ b1
1 ‡ b2
0 ˆ b1

h…2† ˆ y…2† ˆ b₀
0 ‡ b₁
0 ‡ b₂
1 ˆ b₂ h…3† ˆ y…3† ˆ b₀
0 ‡ b₁
0 ‡ b₂
0 ˆ 0 . . .

Therefore the impulse response of the system defined in (3.1.15) is fb₀, b₁, b₂, 0, 0, . . .g.

The I/O equation given in (3.1.15) can be generalized as the difference equation with L parameters, expressed as

y…n† ˆ b0x…n† ‡ b1x…n 1† ‡


‡ bL 1x…n L ‡ 1† ˆX^{L 1}

lˆ0

blx…n l† : …3:1:16†

Substituting x…n† ˆ d…n† into (3.1.16), the output is the impulse response expressed as

h…n† ˆX^{L 1} 1

lˆ0

bld…n l† ˆ b_n n = 0 , 1, ..., L 0 otherwise.



…3:1:17†

Therefore the length of the impulse response is L for the difference equation defined in (3.1.16). Such a system is called a finite impulse response (FIR) system (or filter). The impulse response coefficients, b_l, l ˆ 0, 1, . . . , L 1, are called filter coefficients (weights or taps). The FIR filter coefficients are identical to the impulse response coefficients. Table 3.2 shows the relationship of the FIR filter impulse response h(n) and its coefficients bl.

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