Disadvantages

ROCs can surf over deep voltage fluctuations while sustaining an average performance. This comes at the expense of a clock period with high jitter and potentially large frequency variations. Systems operating with ROCs must tolerate these characteristics along the executing time of the applications.

It is difficult to design an ROC with a stable duty cycle, and the duty cycle cannot be guaranteed. Therefore, this may be a limitation for applications that require both clock edges, such as double data rate (DDR) memories. However, a simple solution is to use multiple clock sources, e.g., a PLL with 50% duty cycle for the memory interface, and ROCs for the random logic.

The GALS methodology has an important characteristic: it requires

cross-domain crossing (CDC) techniques to be applied between the different

ROC regions. There are several known techniques that perform CDC [55]. Each technique has its pros and cons, but there is an overhead in area, power and throughput, independently of the approach defined. Still, for multi-core or very large chips, the use of multiple clocks is already required [107], and the use of multiple ROC domains could be applied without additional costs.

Chapter 6

Conclusions and Future Work

area, and cost (PPAC) using established integrated circuit (IC) manufac-

turing technologies. Advances in electronic design automation (EDA) were investigated in three distinct topics: technology-independent area minimiza- tion, decomposition and remapping methods for field-programmable gate ar-

rays (FPGAs) based on look-up tables (LUTs), and an adaptive clocking

scheme based on ROCs in order to improve performance and power consump- tion of digital circuits, and costs on the PDN design. This chapter presents a summary of the contributions, and provides ideas for future research that can use the present thesis as basis.

6.1

Summary of the thesis contributions

The first contribution is a technology-independent method for area mini- mization of combinational logic, based on a multi-output decomposition us- ing two-literal divisors. An and-inverter graph (AIG) local optimization ap- proach is implemented, applying multi-output Boolean division on KL-cuts. The experiments show promising results, with an average node reduction of 7.8% in comparison with highly optimized AIGs. Similar reductions are ob- served after technology mapping, with area improvements of 5.5% for FPGA mapping, and 6.2% for standard cells.

The second contribution regards the proposition of two methods targeting LUT-based FPGAs: a functional decomposition which uses the support size as cost function, and a recursive remapping. The support-reducing decom- position produces a subject graph with a structure more suitable to FPGA mapping. The recursive remapping approach reduces the structural bias of the circuit, using the actual FPGA mapping result as cost function. The

experiments show very promising results. The combination of the proposed methods improve the FPGA mapping results of a commercial tool for the MCNC benchmarks, with gains of 28% in delay plus 18% in area when tar- geting delay, and 28% in area plus 14% in delay with area as cost function. Average results after physical synthesis show 23% less area and 6% less delay (or 20% less area and 9% less delay) by using the remapping results as in- put to the commercial tool instead of the initial descriptions. In comparison with BoolMap [61], a BDD-based method which takes advantage of another support-reducing decomposition approach, the present work is able to obtain 18% fewer LUTs and 8% fewer logic levels. Moreover, 12 of the best known results for delay (and 6 for area) of the EPFL benchmarks are updated.

Power integrity is a major concern due to low supply voltages and high power density in high-performance circuits. The third contribution consists of an extensive analysis on the dynamic variability mitigation and simpli- fication of PDNs using an adaptive clocking scheme based on ROCs. The analysis shows that ROCs provide a robust clock scheme that tolerates large fluctuations in the supply voltages. ROCs are a competitive alternative to the rigid clocks generated by PLLs, with reductions of up to 83% in perfor- mance margins and up to 27% in leakage power. Notice that the design of a PDN is an arduous task that must consider the circuit characteristics in order to deliver high-quality supply voltages. It was shown that the PDN design constraints can be relaxed, without performance loss, by using an ROC as the clock source. Tolerance to voltage noise and related benefits can also be increased with multiple ROC domains. Additionally, with the increasing importance of the internet of things (IoT), we are facing a future in which many devices will have to operate in environments with scarce en- ergy in which scavenging mechanisms will be essential to survive. Providing reliable supply voltages under these scenarios may be difficult and costly. ROCs emerge as a potential solution to operate robustly in hostile environ- ments with low-cost PDNs. Furthermore, considering the use of integrated circuits in safety-critical applications, the ROCs characteristic of adapting to undesirable operating conditions may be crucial to support situations of limited energy or large voltage noise.